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Name	Last commit message	Last updated
docs	xd74ls93: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	4d ago
viewers	xd74ls93: viewers · Ray	26d ago
package.json	Publish 0.1.0 · Ray	26d ago
page.json	Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray	11d ago
README.md	xd74ls93: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	14d ago
xd74ls93-etched.fit.json	xd74ls93: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	4d ago
xd74ls93-etched.glb	xd74ls93: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	4d ago
xd74ls93-etched.step	xd74ls93: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	4d ago
xd74ls93.glb	Publish 0.1.0 · Ray	26d ago
xd74ls93.kicad_mod	Publish 0.1.0 · Ray	26d ago
xd74ls93.kicad_sym	Publish 0.1.0 · Ray	26d ago
xd74ls93.lbr	Publish 0.1.0 · Ray	26d ago
xd74ls93.step	Publish 0.1.0 · Ray	26d ago

XD74LS93

XINLUDA · Counters, Dividers · DIP-14

XD74LS93 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CKB	input	Clock B input to the divide-by-8 (three-stage) counter section, active on the high-to-low (falling) edge. Drives QB, QC, QD outputs when used stand-alone, or the full 4-bit ripple chain when tied to QA.
2	R0(1)	input	Asynchronous master reset input 1. When both R0(1) and R0(2) are HIGH, all four counter outputs (QA, QB, QC, QD) are forced LOW regardless of the clock inputs.
3	R0(2)	input	Asynchronous master reset input 2. Both R0(1) and R0(2) must be HIGH simultaneously to clear the counter; if either is LOW, normal counting proceeds.
4	NC	unconnected	No internal connection. Leave floating or tie as convenient for layout.
5	VCC	power_in	Positive supply voltage input. Recommended operating range 4.75 V to 5.25 V (5 V nominal); absolute maximum 7 V. Decouple with a 0.1 µF ceramic capacitor close to the pin.
6	NC	unconnected	No internal connection.
7	NC	unconnected	No internal connection.
8	QC	output	Counter output QC - third stage (bit 2, weight 4) of the divide-by-8 ripple section. Toggles on the falling edge of QB.
9	QB	output	Counter output QB - second stage (bit 1, weight 2) of the divide-by-8 ripple section. Toggles on the falling edge of the CKB input.
10	GND	power_in	Ground / 0 V reference for the device. Connect to system ground with a low-impedance path.
11	QD	output	Counter output QD - fourth stage (bit 3, weight 8, MSB) of the divide-by-8 ripple section. Toggles on the falling edge of QC.
12	QA	output	Counter output QA - output of the divide-by-2 flip-flop clocked by CKA. Tie to CKB (pin 1) externally to form a full 4-bit MOD-16 binary counter.
13	NC	unconnected	No internal connection.
14	CKA	input	Clock A input to the independent divide-by-2 flip-flop, active on the high-to-low (falling) edge. Drives QA output.

Key specifications

Parameter	Value
Manufacturer	XINLUDA
Package	DIP-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

XD74LS93N
XD74LS93PC
XD74LS93D
XD74LS93M

CAD (KiCad official)

Symbol: XD74LS93
Footprint: Package_DIP:DIP-14_W7.62mm
3D model: DIP-14 (KiCad packages3D, STEP)
3D model files: xd74ls93-etched.step / xd74ls93-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls93.step / xd74ls93.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XINLUDA datasheet (8 pp, sha256 d9adfc947b748a32, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF