XD74LS93

@@ -1,13 +1,180 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "xd74ls93",+  "title": "XD74LS93",+  "brief": "XINLUDA Counters, Dividers, DIP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "XINLUDA Counters, Dividers, DIP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "xd74ls93"   ],+  "component": {+    "mpn": "XD74LS93",+    "manufacturer": "XINLUDA",+    "package": "DIP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Counters, Dividers",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590163850835632128",+    "parts": {+      "symbol": "xd74ls93.kicad_sym",+      "footprint": "xd74ls93.kicad_mod",+      "model_3d": "xd74ls93.glb",+      "model_3d_step": "xd74ls93.step",+      "lbr": "xd74ls93.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "CKB",+        "type": "input",+        "description": "Clock B input to the divide-by-8 (three-stage) counter section, active on the high-to-low (falling) edge. Drives QB, QC, QD outputs when used stand-alone, or the full 4-bit ripple chain when tied to QA."+      },+      {+        "number": "2",+        "name": "R0(1)",+        "type": "input",+        "description": "Asynchronous master reset input 1. When both R0(1) and R0(2) are HIGH, all four counter outputs (QA, QB, QC, QD) are forced LOW regardless of the clock inputs."+      },+      {+        "number": "3",+        "name": "R0(2)",+        "type": "input",+        "description": "Asynchronous master reset input 2. Both R0(1) and R0(2) must be HIGH simultaneously to clear the counter; if either is LOW, normal counting proceeds."+      },+      {+        "number": "4",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection. Leave floating or tie as convenient for layout."+      },+      {+        "number": "5",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage input. Recommended operating range 4.75 V to 5.25 V (5 V nominal); absolute maximum 7 V. Decouple with a 0.1 \u00b5F ceramic capacitor close to the pin."+      },+      {+        "number": "6",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection."+      },+      {+        "number": "7",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection."+      },+      {+        "number": "8",+        "name": "QC",+        "type": "output",+        "description": "Counter output QC - third stage (bit 2, weight 4) of the divide-by-8 ripple section. Toggles on the falling edge of QB."+      },+      {+        "number": "9",+        "name": "QB",+        "type": "output",+        "description": "Counter output QB - second stage (bit 1, weight 2) of the divide-by-8 ripple section. Toggles on the falling edge of the CKB input."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Ground / 0 V reference for the device. Connect to system ground with a low-impedance path."+      },+      {+        "number": "11",+        "name": "QD",+        "type": "output",+        "description": "Counter output QD - fourth stage (bit 3, weight 8, MSB) of the divide-by-8 ripple section. Toggles on the falling edge of QC."+      },+      {+        "number": "12",+        "name": "QA",+        "type": "output",+        "description": "Counter output QA - output of the divide-by-2 flip-flop clocked by CKA. Tie to CKB (pin 1) externally to form a full 4-bit MOD-16 binary counter."+      },+      {+        "number": "13",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection."+      },+      {+        "number": "14",+        "name": "CKA",+        "type": "input",+        "description": "Clock A input to the independent divide-by-2 flip-flop, active on the high-to-low (falling) edge. Drives QA output."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590163850835632128",+        "pages": 8,+        "sha256": "d9adfc947b748a32",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "XINLUDA",+      "Package": "DIP-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "variants": [+    {+      "mpn": "XD74LS93N",+      "kind": "packaging"+    },+    {+      "mpn": "XD74LS93PC",+      "kind": "packaging"+    },+    {+      "mpn": "XD74LS93D",+      "kind": "packaging"+    },+    {+      "mpn": "XD74LS93M",+      "kind": "packaging"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "xd74ls93"+  ],+  "discovery_pitch": "XD74LS93 (XINLUDA) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +192,5 @@     "docs/xd74ls93-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file