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XD74LS90

XINLUDA · Counters, Dividers · DIP-14

XD74LS90 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CKB input Clock B input for the divide-by-five section (QB, QC, QD); connect to QA for full decade count, with count frequency 0 to 16 MHz.
2 R0(1) input Gated zero reset input; with R0(2) high (and R9 inputs not both high) it resets outputs QD QC QB QA to LLLL.
3 R0(2) input Gated zero reset input; with R0(1) high (and R9 inputs not both high) it resets outputs QD QC QB QA to LLLL.
4 NC unconnected No internal connection.
5 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (nominal 5 V), absolute maximum 7 V.
6 R9(1) input Gated set-to-nine input; with R9(2) high it sets outputs QD QC QB QA to HLLH (BCD 9).
7 R9(2) input Gated set-to-nine input; with R9(1) high it sets outputs QD QC QB QA to HLLH (BCD 9).
8 QC output Counter output C, rated for 8 mA low-level and -400 uA high-level output current.
9 QB output Counter output B, rated for 8 mA low-level and -400 uA high-level output current.
10 GND power_in Ground, the network ground terminal to which voltage values are referenced.
11 QD output Counter output D (MSB); can be connected to CKA for a symmetrical divide-by-ten, rated 8 mA low-level and -400 uA high-level output current.
12 QA output Counter output A (LSB) of the divide-by-two section, rated 8 mA low-level and -400 uA high-level output current.
13 NC unconnected No internal connection.
14 CKA input Clock A input for the divide-by-two section; count frequency 0 to 32 MHz.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (Note 1: with respect to network ground) VCC 7 V see Note 1 5
Input voltage (74LS90) VI 7 V 74LS90 5
Operating free-air temperature range TA 0 70 °C DIP package 5
Storage temperature range Tstg -65 150 °C 5
Supply voltage VCC 4.75 5 5.25 V 6
High-level output current IOH -400 μA 6
Low-level output current IOL 8 mA 6
Count frequency, A input fcount 0 32 MHz A input 6
Count frequency, B input fcount 0 16 MHz B input 6
Pulse duration, A input tw 15 ns A input 6
Pulse duration, B input tw 30 ns B input 6
Pulse duration, reset inputs tw 30 ns Reset inputs 6
Reset inactive-state setup time tsu 25 ns Reset inactive state 6
Operating free-air temperature TA 0 70 °C 6
High-level input voltage VIH 2 V 6
Low-level input voltage VIL 0.8 V 6
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 6
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = VIL MAX, VIH = 2 V, IOH = −400 μA 6
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 1.6 mA 6
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 3.2 mA 6
Input current at maximum input voltage, any reset II 0.1 mA VCC = MAX, VI = 7 V 6
Input current at maximum input voltage, CKA II 0.2 mA VCC = MAX, VI = 5.5 V 6
Input current at maximum input voltage, CKB II 0.4 mA VCC = MAX, VI = 5.5 V 6
High-level input current, any reset IIH 20 μA VCC = MAX, VI = 2.7 V 6
High-level input current, CKA IIH 40 μA VCC = MAX, VI = 2.7 V 6
High-level input current, CKB IIH 80 μA VCC = MAX, VI = 2.7 V 6
Low-level input current, any reset IIL -0.4 mA VCC = MAX, VI = 0.4 V 6
Low-level input current, CKA IIL -2.4 mA VCC = MAX, VI = 0.4 V 6
Low-level input current, CKB IIL -3.2 mA VCC = MAX, VI = 0.4 V 6
Short-circuit output current IOS -20 -100 mA VCC = MAX 6
Supply current ICC 9 15 mA VCC = MAX 6
Maximum count frequency, CKA to QA fmax 32 42 MHz VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Maximum count frequency, CKB to QB fmax 16 MHz VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay low-to-high, CKA to QA tPLH 10 16 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay high-to-low, CKA to QA tPHL 12 18 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay low-to-high, CKA to QD tPLH 32 48 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay high-to-low, CKA to QD tPHL 34 50 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay low-to-high, CKB to QB tPLH 10 16 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay high-to-low, CKB to QB tPHL 14 21 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay low-to-high, CKB to QC tPLH 21 32 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay high-to-low, CKB to QC tPHL 23 35 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay low-to-high, CKB to QD tPLH 21 32 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay high-to-low, CKB to QD tPHL 23 35 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay high-to-low, set-to-0 to any output tPHL 26 40 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay low-to-high, set-to-9 to QA, QD tPLH 20 30 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7
Propagation delay high-to-low, set-to-9 to QB, QC tPHL 26 40 ns VCC = 5 V, TA = 25 °C, CL = 15 pF, RL = 2 kΩ 7

CAD (KiCad official)

  • Symbol: XD74LS90
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls90-etched.step / xd74ls90-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls90.step / xd74ls90.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (8 pp, sha256 9cdc8f286458d58c, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF