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XD74LS83

Public Made by Adom

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XINLUDA Flip Flops, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD74LS83

XINLUDA · Flip Flops · DIP-16

XD74LS83 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A4 input Word A input bit 4 of the 4-bit adder; VIH min 2.0 V, VIL max 0.8 V.
2 Σ3 output Sum output for bit 3; VOH min 2.7 V at IOH = -400 µA, VOL max 0.5 V at IOL = 8 mA.
3 A3 input Word A input bit 3 of the 4-bit adder; VIH min 2.0 V, VIL max 0.8 V.
4 B3 input Word B input bit 3 of the 4-bit adder; VIH min 2.0 V, VIL max 0.8 V.
5 VCC power_in Supply voltage, 4.75 V to 5.25 V recommended (typ 5.00 V), 7 V absolute maximum.
6 Σ2 output Sum output for bit 2; VOH min 2.7 V at IOH = -400 µA, VOL max 0.5 V at IOL = 8 mA.
7 B2 input Word B input bit 2 of the 4-bit adder; VIH min 2.0 V, VIL max 0.8 V.
8 A2 input Word A input bit 2 of the 4-bit adder; VIH min 2.0 V, VIL max 0.8 V.
9 Σ1 output Sum output for bit 1; VOH min 2.7 V at IOH = -400 µA, VOL max 0.5 V at IOL = 8 mA.
10 A1 input Word A input bit 1 of the 4-bit adder; VIH min 2.0 V, VIL max 0.8 V.
11 B1 input Word B input bit 1 of the 4-bit adder; VIH min 2.0 V, VIL max 0.8 V.
12 GND power_in Ground (0 V) reference.
13 C0 input Carry input to the first bit; IIH max 20 µA at 2.7 V and IIL max -0.4 mA at 0.4 V.
14 C4 output Carry output from the fourth bit, about 10 ns typical carry generation via full internal look-ahead.
15 Σ4 output Sum output for bit 4; VOH min 2.7 V at IOH = -400 µA, VOL max 0.5 V at IOL = 8 mA.
16 B4 input Word B input bit 4 of the 4-bit adder; VIH min 2.0 V, VIL max 0.8 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V 4
Input voltage VIN 7 V 4
Power dissipation PT 400 mW 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 4.75 5 5.25 V 4
Output current, high level IOH -400 A 4
Output current, low level IOL 8 mA 4
Operating temperature Topr 0 70 °C 4
Input voltage, high level VIH 2 V Ta = 0 to +70 °C 4
Input voltage, low level VIL 0.8 V Ta = 0 to +70 °C 4
Output voltage, high level VOH 2.7 V Ta = 0 to +70 °C; VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A 4
Output voltage, low level VOL 0.4 V Ta = 0 to +70 °C; IOL = 4 mA, VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V 4
Output voltage, low level VOL 0.5 V Ta = 0 to +70 °C; IOL = 8 mA, VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V 4
Input current, high level, except C0 IIH 40 A Ta = 0 to +70 °C; except C0; VCC = 5.25 V, VI = 2.7 V 4
Input current, high level, C0 IIH 20 A Ta = 0 to +70 °C; C0; VCC = 5.25 V, VI = 2.7 V 4
Input current, low level, except C0 IIL -0.8 mA Ta = 0 to +70 °C; except C0; VCC = 5.25 V, VI = 0.4 V 4
Input current, low level, C0 IIL -0.4 mA Ta = 0 to +70 °C; C0; VCC = 5.25 V, VI = 0.4 V 4
Input current, maximum, except C0 II 0.2 mA Ta = 0 to +70 °C; except C0; VCC = 5.25 V, VI = 7 V 4
Input current, maximum, C0 II 0.1 mA Ta = 0 to +70 °C; C0; VCC = 5.25 V, VI = 7 V 4
Short-circuit output current IOS -20 -100 mA Ta = 0 to +70 °C; VCC = 5.25 V 4
Supply current ICC 22 39 mA Ta = 0 to +70 °C; test condition not clearly printed for this row 4
Supply current, all inputs at 0 V ICC 19 34 mA Ta = 0 to +70 °C; All inputs = 0 V; VCC = 5.25 V 4
Supply current, B input at 0.8 V ICC 19 34 mA Ta = 0 to +70 °C; B input = 0.8 V, other inputs 4.5 V 4
Input clamp voltage VIR -1.5 V Ta = 0 to +70 °C; VCC = 4.75 V, IIN = -18 mA 4
Propagation delay time, low-to-high, C0 to output 1 tPLH 16 24 ns VCC = 5 V, Ta = 25°C, CL = 15 pF, RL = 2 k 5
Propagation delay time, high-to-low, C0 to output 1 tPHL 15 24 ns VCC = 5 V, Ta = 25°C, CL = 15 pF, RL = 2 k 5
Propagation delay time, low-to-high, Ai/Bi to output 1 tPLH 15 24 ns VCC = 5 V, Ta = 25°C, CL = 15 pF, RL = 2 k 5
Propagation delay time, high-to-low, Ai/Bi to output 1 tPHL 15 24 ns VCC = 5 V, Ta = 25°C, CL = 15 pF, RL = 2 k 5
Propagation delay time, low-to-high, C0 to C4 tPLH 11 17 ns VCC = 5 V, Ta = 25°C, CL = 15 pF, RL = 2 k 5
Propagation delay time, high-to-low, C0 to C4 tPHL 15 22 ns VCC = 5 V, Ta = 25°C, CL = 15 pF, RL = 2 k 5
Propagation delay time, low-to-high, Ai/Bi to C4 tPLH 11 17 ns VCC = 5 V, Ta = 25°C, CL = 15 pF, RL = 2 k 5
Propagation delay time, high-to-low, Ai/Bi to C4 tPHL 12 17 ns VCC = 5 V, Ta = 25°C, CL = 15 pF, RL = 2 k 5

CAD (KiCad official)

  • Symbol: XD74LS83
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd74ls83-etched.step / xd74ls83-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls83.step / xd74ls83.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (8 pp, sha256 fdb4387908d31ba2, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF