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XD74LS75

Public Made by Adom

by adom

XINLUDA Latches, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD74LS75

XINLUDA · Latches · DIP-16

XD74LS75 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Q̅ output Complementary output of latch 1; high-level output current up to -400 µA and low-level up to 4 mA.
2 1D input Data input of latch 1, transferred to 1Q while enable 1C,2C is high.
3 2D input Data input of latch 2, transferred to 2Q while enable 1C,2C is high.
4 3C,4C input Common enable input for latches 3 and 4; data passes when high and is retained when low.
5 VCC power_in Supply voltage, 4.75 V to 5.25 V recommended (5 V nominal), 7 V absolute maximum.
6 3D input Data input of latch 3, transferred to 3Q while enable 3C,4C is high.
7 4D input Data input of latch 4, transferred to 4Q while enable 3C,4C is high.
8 4Q̅ output Complementary output of latch 4; high-level output current up to -400 µA and low-level up to 4 mA.
9 4Q output True output of latch 4; high-level output current up to -400 µA and low-level up to 4 mA.
10 3Q output True output of latch 3; high-level output current up to -400 µA and low-level up to 4 mA.
11 3Q̅ output Complementary output of latch 3; high-level output current up to -400 µA and low-level up to 4 mA.
12 GND power_in Ground terminal, reference for all voltages.
13 1C,2C input Common enable input for latches 1 and 2; data passes when high and is retained when low.
14 2Q̅ output Complementary output of latch 2; high-level output current up to -400 µA and low-level up to 4 mA.
15 2Q output True output of latch 2; high-level output current up to -400 µA and low-level up to 4 mA.
16 1Q output True output of latch 1; high-level output current up to -400 µA and low-level up to 4 mA.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (see Note 1) VCC 7 V See Note 1 4
Input voltage (74LS75) VI 7 V 4
Operating free-air temperature range TA 0 70 °C DIP package 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VCC 4.75 5 5.25 V 5
High-level output current IOH -400 μA 5
Low-level output current IOL 4 mA 5
Width of enabling pulse tw 20 ns 5
Setup time tsu 20 ns 5
Hold time th 5 ns 5
Operating free-air temperature TA 0 70 °C 5
High-level input voltage VIH 2 V 5
Low-level input voltage VIL 0.8 V 5
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 5
High-level output voltage VOH 2.7 3.5 V VCC = MIN, VIL = MAX, IOH = −400μA 5
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, IOL = 4 mA 5
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, IOL = 8 mA 5
Input current (D input) II 0.1 mA VCC = MAX, VI = 7 V, D input 5
Input current (C input) II 0.4 mA VCC = MAX, VI = 7 V, C input 5
High-level input current (D input) IIH 20 μA VCC = MAX, VI = 2.7 V, D input 5
High-level input current (C input) IIH 80 μA VCC = MAX, VI = 2.7 V, C input 5
Low-level input current (D input) IIL -0.4 mA VCC = MAX, VI = 0.4 V, D input 5
Low-level input current (C input) IIL -1.6 mA VCC = MAX, VI = 0.4 V, C input 5
Short-circuit output current IOS -20 -100 mA VCC = MAX 5
Supply current ICC 6.3 12 mA VCC = MAX, See note2 5
Propagation delay, D to Q tPLH 15 27 ns RL = 2 kΩ, CL = 15 pF, See Figure 1 6
Propagation delay, D to Q tPHL 9 17 ns RL = 2 kΩ, CL = 15 pF, See Figure 1 6
Propagation delay, D to output (label not legible) tPHL 12 20 ns RL = 2 kΩ, CL = 15 pF, See Figure 1 6
Propagation delay, D to output (label not legible) tPHL 7 15 ns RL = 2 kΩ, CL = 15 pF, See Figure 1 6
Propagation delay, C to Q tPHL 15 27 ns RL = 2 kΩ, CL = 15 pF, See Figure 1 6
Propagation delay, C to Q tPHL 14 25 ns RL = 2 kΩ, CL = 15 pF, See Figure 1 6
Propagation delay, C to output (label not legible) tPHL 16 30 ns RL = 2 kΩ, CL = 15 pF, See Figure 1 6
Propagation delay, C to output (label not legible) tPHL 7 15 ns RL = 2 kΩ, CL = 15 pF, See Figure 1 6

CAD (KiCad official)

  • Symbol: XD74LS75
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd74ls75-etched.step / xd74ls75-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls75.step / xd74ls75.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (7 pp, sha256 a70fe69490d2e982, retrieved 2026-10-14, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF