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XD74LS73

Public Made by Adom

by adom

XINLUDA Flip Flops, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD74LS73

XINLUDA · Flip Flops · DIP-14

XD74LS73 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLK input Clock input of flip-flop 1, triggered on the high-to-low transition.
2 1CLR input Active-low clear of flip-flop 1; when low it overrides clock and data inputs, forcing Q low and Q-bar high.
3 1K input K data input of flip-flop 1, which must be stable one setup time before the high-to-low clock transition.
4 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V.
5 2CLK input Clock input of flip-flop 2, triggered on the high-to-low transition.
6 2CLR input Active-low clear of flip-flop 2; when low it overrides clock and data inputs, forcing Q low and Q-bar high.
7 2J input J data input of flip-flop 2, which must be stable one setup time before the high-to-low clock transition.
8 2Q̅ output Complementary output of flip-flop 2, high when its clear is low.
9 2Q output True output of flip-flop 2, forced low when its clear is low.
10 2K input K data input of flip-flop 2, which must be stable one setup time before the high-to-low clock transition.
11 GND power_in Ground terminal, reference for the voltage values.
12 1Q output True output of flip-flop 1, forced low when its clear is low.
13 1Q̅ output Complementary output of flip-flop 1, high when its clear is low.
14 1J input J data input of flip-flop 1, which must be stable one setup time before the high-to-low clock transition.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V 4
High-level input voltage VIH 2 V 4
Clock frequency fclock 0 8 MHz 4
Pulse duration CLK high tw 20 ns CLK high 4
Pulse duration CLR low tw 20 ns CLR low 4
Setup time before CLK↓ tsu 20 ns Data high or low 4
Hold time, data after CLK↓ th 0 ns 4
Operating free-air temperature TA 0 70 °C 4
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 4
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIH = 2 V, IOH = 4mA 4
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 8mA 4
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 8mA 4
Input current at maximum input voltage, J or K II 0.1 mA VCC = MAX, VI = 7 V 4
Input current at maximum input voltage, CLR II 0.3 mA VCC = MAX, VI = 7 V 4
Input current at maximum input voltage, CLK II 0.4 mA VCC = MAX, VI = 7 V 4
High-level input current, J or K IIH 20 µA VCC = MAX, VI = 2.7 V 4
High-level input current, CLR IIH 60 µA VCC = MAX, VI = 2.7 V 4
High-level input current, CLK IIH 80 µA VCC = MAX, VI = 2.7 V 4
Low-level input current, J or K IIL -0.4 mA VCC = MAX, VI = 0.4 V 4
Low-level input current, CLR or CLK IIL -0.8 mA VCC = MAX, VI = 0.4 V 4
Short-circuit output current IOS -20 -100 mA VCC = MAX 4
Supply current (total) ICC 4 6 mA VCC = MAX 4
Maximum clock frequency fmax 30 45 MHz CL=15 pF, RL=2kΩ, See Note 3 4
Propagation delay low-to-high tPLH 15 20 ns VCC = 5 V, TA = 25℃ 4
Propagation delay high-to-low tPHL 15 20 ns VCC = 5 V, TA = 25℃ 4
Supply voltage VCC 7 V 3
Input voltage, 74LS73 VI 7 V 74LS73 3
Storage temperature range Tstg -65 150 °C 3

CAD (KiCad official)

  • Symbol: XD74LS73
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls73-etched.step / xd74ls73-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls73.step / xd74ls73.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 a9fcde1c9a1134ee, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF