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XD74LS54

Public Made by Adom

by adom

XINLUDA Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD74LS54

XINLUDA · Gates · DIP-14

XD74LS54 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input AND gate 1 input A (with B); input high level min 2 V, low level max 0.8 V.
2 B input AND gate 1 input B (with A); input high level min 2 V, low level max 0.8 V.
3 C input AND gate 2 input C (with D and E); input high level min 2 V, low level max 0.8 V.
4 D input AND gate 2 input D (with C and E); input high level min 2 V, low level max 0.8 V.
5 E input AND gate 2 input E (with C and D); input high level min 2 V, low level max 0.8 V.
6 Y output Inverted AND-OR output Y = !(AB + CDE + FGH + IJ); IOH -0.4 mA max, IOL 8 mA max.
7 GND power_in Ground reference for the supply and all voltages.
8 NC unconnected No internal connection.
9 F input AND gate 3 input F (with G and H); input high level min 2 V, low level max 0.8 V.
10 G input AND gate 3 input G (with F and H); input high level min 2 V, low level max 0.8 V.
11 H input AND gate 3 input H (with F and G); input high level min 2 V, low level max 0.8 V.
12 I input AND gate 4 input I (with J); input high level min 2 V, low level max 0.8 V.
13 J input AND gate 4 input J (with I); input high level min 2 V, low level max 0.8 V.
14 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
High-level output current IOH -0.4 mA 4
Low-level output current IOL 8 mA 4
Operating free-air temperature TA 0 70 C 4
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 4
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = MAX, IOH = −0.4 mA 4
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, IOL = 4 mA 4
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, IOL = 8 mA 4
Input current at maximum input voltage II 0.1 mA VCC = MAX, VI = 7 V 4
High-level input current IIH 20 A VCC = MAX, VI = 2.7 V 4
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 4
Short-circuit output current IOS -100 -20 mA VCC = MAX 4
Supply current, outputs high ICCH 0.8 1.6 mA VCC = MAX, VI = 4.5 V 4
Supply current, outputs low ICCL 1.4 2.8 mA VCC = MAX, VI = 0 V 4
Propagation delay, low-to-high tPLH 12 20 ns VCC = 5 V, TA = 25℃, RL = 2 kΩ, CL = 15 pF, Any to Y 4
Propagation delay, high-to-low tPHL 12.5 20 ns VCC = 5 V, TA = 25℃, RL = 2 kΩ, CL = 15 pF, Any to Y 4
Supply voltage VCC 7 V see Note 1 3
Input voltage VI 7 V 74LS54 3
Operating free-air temperature range 0 70 C DIP package 3
Storage temperature range Tstg -65 150 C 3

CAD (KiCad official)

  • Symbol: XD74LS54
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls54-etched.step / xd74ls54-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls54.step / xd74ls54.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 2e47d5fcdaf4f12f, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF