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XD74LS32

XINLUDA · Gates · DIP-14

XD74LS32 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A; output 1Y is high when either 1A or 1B is high (VIH min 2 V, VIL max 0.8 V).
2 1B input Gate 1 input B; output 1Y is high when either 1A or 1B is high (VIH min 2 V, VIL max 0.8 V).
3 1Y output Gate 1 output, the OR of 1A and 1B (IOH -0.4 mA, IOL 8 mA max).
4 2A input Gate 2 input A; output 2Y is high when either 2A or 2B is high (VIH min 2 V, VIL max 0.8 V).
5 2B input Gate 2 input B; output 2Y is high when either 2A or 2B is high (VIH min 2 V, VIL max 0.8 V).
6 2Y output Gate 2 output, the OR of 2A and 2B (IOH -0.4 mA, IOL 8 mA max).
7 GND power_in Ground reference for the device; voltage values are specified with respect to this terminal.
8 3Y output Gate 3 output, the OR of 3A and 3B (IOH -0.4 mA, IOL 8 mA max).
9 3A input Gate 3 input A; output 3Y is high when either 3A or 3B is high (VIH min 2 V, VIL max 0.8 V).
10 3B input Gate 3 input B; output 3Y is high when either 3A or 3B is high (VIH min 2 V, VIL max 0.8 V).
11 4Y output Gate 4 output, the OR of 4A and 4B (IOH -0.4 mA, IOL 8 mA max).
12 4A input Gate 4 input A; output 4Y is high when either 4A or 4B is high (VIH min 2 V, VIL max 0.8 V).
13 4B input Gate 4 input B; output 4Y is high when either 4A or 4B is high (VIH min 2 V, VIL max 0.8 V).
14 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V see Note 1 2
Input voltage VI 7 V 74LS32 2
Storage temperature range Tstg -65 150 C 2
Operating free-air temperature range, DIP package 0 70 C DIP package 2
Supply voltage VCC 4.75 5 5.25 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
High-level output current IOH -0.4 mA 3
Low-level output current IOL 8 mA 3
Operating free-air temperature TA 0 70 C 3
Input clamp voltage VIK -1.5 V VCC = MIN, II = -18 mA 3
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = MAX, IOH = -0.4 mA 3
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, IOL = 4 mA 3
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, IOL = 8 mA 3
Input current at maximum input voltage II 0.1 mA VCC = MAX, VI = 7 V 3
High-level input current IIH 20 A VCC = MAX, VI = 2.7 V 3
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 3
Short-circuit output current IOS -20 -100 mA VCC = MAX 3
Supply current, outputs high ICCH 3.1 6.2 mA VCC = MAX, VI = 4.5 V 3
Supply current, outputs low ICCL 4.9 9.8 mA VCC = MAX, VI = 0 V 3
Propagation delay time, low-to-high output, A or B to Y tPLH 14 22 ns RL = 2 kΩ, CL = 15 pF, VCC = 5 V, TA = 25℃ 3
Propagation delay time, high-to-low output, A or B to Y tPHL 14 22 ns RL = 2 kΩ, CL = 15 pF, VCC = 5 V, TA = 25℃ 3

CAD (KiCad official)

  • Symbol: XD74LS32
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls32-etched.step / xd74ls32-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls32.step / xd74ls32.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 b7740cc2b3228b00, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF