component
XD74LS27
Public Made by Adomby adom
XINLUDA Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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XD74LS27
XINLUDA · Logic Gates · DIP-14
XD74LS27 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A; output 1Y is low if any of 1A, 1B, 1C is high (VIH min 2 V, VIL max 0.8 V). |
| 2 | 1B | input | Gate 1 input B of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 3 | 2A | input | Gate 2 input A of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 4 | 2B | input | Gate 2 input B of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 5 | 2C | input | Gate 2 input C of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 6 | 2Y | output | Gate 2 output, Y = NOT(A+B+C); high-level output current -0.4 mA max, low-level 8 mA max. |
| 7 | GND | power_in | Ground reference (0 V). |
| 8 | 3Y | output | Gate 3 output, Y = NOT(A+B+C); high-level output current -0.4 mA max, low-level 8 mA max. |
| 9 | 3A | input | Gate 3 input A of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 10 | 3B | input | Gate 3 input B of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 11 | 3C | input | Gate 3 input C of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 12 | 1Y | output | Gate 1 output, Y = NOT(A+B+C); high-level output current -0.4 mA max, low-level 8 mA max. |
| 13 | 1C | input | Gate 1 input C of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 14 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
XD74LS27 - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
xd74ls27-etched.step/xd74ls27-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd74ls27.step/xd74ls27.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (4 pp, sha256
ab26c9b50c7f2ed5, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# XD74LS27
**XINLUDA** · Logic Gates · DIP-14
XD74LS27 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A; output 1Y is low if any of 1A, 1B, 1C is high (VIH min 2 V, VIL max 0.8 V). |
| 2 | 1B | input | Gate 1 input B of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 3 | 2A | input | Gate 2 input A of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 4 | 2B | input | Gate 2 input B of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 5 | 2C | input | Gate 2 input C of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 6 | 2Y | output | Gate 2 output, Y = NOT(A+B+C); high-level output current -0.4 mA max, low-level 8 mA max. |
| 7 | GND | power_in | Ground reference (0 V). |
| 8 | 3Y | output | Gate 3 output, Y = NOT(A+B+C); high-level output current -0.4 mA max, low-level 8 mA max. |
| 9 | 3A | input | Gate 3 input A of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 10 | 3B | input | Gate 3 input B of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 11 | 3C | input | Gate 3 input C of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 12 | 1Y | output | Gate 1 output, Y = NOT(A+B+C); high-level output current -0.4 mA max, low-level 8 mA max. |
| 13 | 1C | input | Gate 1 input C of the 3-input NOR gate (VIH min 2 V, VIL max 0.8 V). |
| 14 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `XD74LS27`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files: `xd74ls27-etched.step` / `xd74ls27-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xd74ls27.step` / `xd74ls27.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913975228567552) (4 pp, sha256 `ab26c9b50c7f2ed5`, retrieved 2026-10-15, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/xd74ls27-datasheet.pdf)