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XD74LS21

Public Made by Adom

by adom

XINLUDA Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD74LS21

XINLUDA · Gates · DIP-14

XD74LS21 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A; input high level min 2 V, low level max 0.8 V, absolute max input voltage 7 V.
2 1B input Gate 1 input B; input high level min 2 V, low level max 0.8 V, absolute max input voltage 7 V.
3 NC unconnected No internal connection.
4 1C input Gate 1 input C; input high level min 2 V, low level max 0.8 V, absolute max input voltage 7 V.
5 1D input Gate 1 input D; input high level min 2 V, low level max 0.8 V, absolute max input voltage 7 V.
6 1Y output Gate 1 NAND output (Y = NOT(A·B·C·D)); IOH max −0.4 mA, IOL max 8 mA.
7 GND power_in Ground, reference for all voltages.
8 2Y output Gate 2 NAND output (Y = NOT(A·B·C·D)); IOH max −0.4 mA, IOL max 8 mA.
9 2A input Gate 2 input A; input high level min 2 V, low level max 0.8 V, absolute max input voltage 7 V.
10 2B input Gate 2 input B; input high level min 2 V, low level max 0.8 V, absolute max input voltage 7 V.
11 NC unconnected No internal connection.
12 2C input Gate 2 input C; input high level min 2 V, low level max 0.8 V, absolute max input voltage 7 V.
13 2D input Gate 2 input D; input high level min 2 V, low level max 0.8 V, absolute max input voltage 7 V.
14 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute max 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
High-level output current IOH -0.4 mA 4
Low-level output current IOL 8 mA 4
Operating free-air temperature TA 0 70 C 4
Supply voltage VCC 7 V see Note 1 3
Input voltage VI 7 V 74LS21 3
Storage temperature range Tstg -65 150 C 3
Input clamp voltage VIK -1.5 V VCC = MIN, II = -18 mA 4
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = MAX, IOH = -0.4 mA 4
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, IOL = 4 mA 4
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, IOL = 8 mA 4
Input current at max input voltage II 0.1 mA VCC = MAX, VI = 7 V 4
High-level input current IIH 20 A VCC = MAX, VI = 2.7 V 4
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 4
Short-circuit output current IOS -20 -100 mA VCC = MAX 4
Supply current, outputs high ICCH 1.2 2.4 mA VCC = MAX, VI = 4.5 V 4
Supply current, outputs low ICCL 2.2 4.4 mA VCC = MAX, VI = 0 V 4
Propagation delay, low-to-high tPLH 8 15 ns VCC = 5 V, TA = 25 C, RL = 2 kΩ, CL = 15 pF 4
Propagation delay, high-to-low tPHL 10 20 ns VCC = 5 V, TA = 25 C, RL = 2 kΩ, CL = 15 pF 4

CAD (KiCad official)

  • Symbol: XD74LS21
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls21-etched.step / xd74ls21-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls21.step / xd74ls21.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 cf7e6a3bd695af18, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF