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XD74LS194

Public Made by Adom

by adom

XINLUDA Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD74LS194

XINLUDA · Shift Registers · DIP-16

XD74LS194 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low direct overriding clear input that sets all outputs QA-QD low regardless of clock.
2 SR SER input Shift-right serial data input, entered on the rising clock edge when S0 is high and S1 is low.
3 A input Parallel data input A, loaded into QA on the rising clock edge when S0 and S1 are both high.
4 B input Parallel data input B, loaded into QB on the rising clock edge when S0 and S1 are both high.
5 C input Parallel data input C, loaded into QC on the rising clock edge when S0 and S1 are both high.
6 D input Parallel data input D, loaded into QD on the rising clock edge when S0 and S1 are both high.
7 SL SER input Shift-left serial data input, entered on the rising clock edge when S0 is low and S1 is high.
8 GND power_in Ground supply pin.
9 S0 input Mode control input S0, which together with S1 selects hold, shift right, shift left or parallel load.
10 S1 input Mode control input S1, which together with S0 selects hold, shift right, shift left or parallel load.
11 CLK input Clock input, positive-edge triggered.
12 QD output Register output D, the last stage in the shift-right direction, with IOL up to 8 mA.
13 QC output Register output C, with IOL up to 8 mA.
14 QB output Register output B, with IOL up to 8 mA.
15 QA output Register output A, the first stage in the shift-right direction, with IOL up to 8 mA.
16 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V, absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V 6
High-level output current IOH -400 μA 6
Low-level output current IOL 8 mA 6
Clock frequency fclock 0 25 MHz 6
Width of any input pulse tw 20 ns 6
Clear inactive-state setup time tsu 30 ns 6
Load inactive-state setup time tsu 20 ns 6
Data setup time tsu 25 ns 6
Data hold time th 0 ns 6
Operating free-air temperature range TA 0 70 C 6
Supply voltage VCC 7 V 5
Input voltage VI 7 V 74LS194 5
Operating free-air temperature range 0 70 C DIP package 5
Storage temperature range Tstg -65 150 C 5
High-level input voltage VIH 2 V 6
Low-level input voltage VIL 0.8 V 6
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 6
High-level output voltage VOH 2.7 3.5 V VCC = MIN, VIL = VIL MAX, VIH = 2 V, IOH = −400 μA 6
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 4 mA 6
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 8 mA 6
Input current at maximum input voltage II 0.1 mA VCC = MAX, VI = 7 V 6
High-level input current IIH 20 μA VCC = MAX, VI = 2.7 V 6
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 6
Short-circuit output current IOS -20 -100 mA VCC = MAX 6
Supply current ICC 15 23 mA VCC = MAX 6
Maximum clock frequency fMAX 25 36 MHz 7
Propagation delay time, high-to-low-level output from clear tPHL 19 30 ns CL = 15 pF, RL = 2 k 7
Propagation delay time, low-to-high-level output from clear tPLH 14 22 ns CL = 15 pF, RL = 2 k 7
Propagation delay time, high-to-low-level output (third row) tPHL 17 26 ns CL = 15 pF, RL = 2 k 7

CAD (KiCad official)

  • Symbol: XD74LS194
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd74ls194-etched.step / xd74ls194-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls194.step / xd74ls194.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (8 pp, sha256 e42c5501ce740d86, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF