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XD74LS160

Public Made by Adom

by adom

XINLUDA Counters / Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD74LS160

XINLUDA · Counters / Dividers · DIP-16

XD74LS160 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low clear input; on the 'LS160 it asynchronously sets all four outputs low regardless of clock, load or enable inputs.
2 CLK input Buffered clock input that triggers the four flip-flops on the rising edge of the clock waveform.
3 A input Data input A for presetting the counter, loaded synchronously when LOAD is low.
4 B input Data input B for presetting the counter, loaded synchronously when LOAD is low.
5 C input Data input C for presetting the counter, loaded synchronously when LOAD is low.
6 D input Data input D for presetting the counter, loaded synchronously when LOAD is low.
7 ENP input Count-enable P input; with ENT it enables counting and may change regardless of the clock level.
8 GND power_in Ground pin.
9 LOAD input Active-low synchronous load input; a low level disables counting and loads the outputs from the data inputs after the next clock pulse regardless of the enable inputs.
10 ENT input Count-enable T input; it also gates the ripple carry output RCO and may change regardless of the clock level.
11 QD output Counter output D (most significant bit); low-level output current rated 8 mA.
12 QC output Counter output C; low-level output current rated 8 mA.
13 QB output Counter output B; low-level output current rated 8 mA.
14 QA output Counter output A (least significant bit); low-level output current rated 8 mA.
15 RCO output Ripple carry output giving a high pulse about as long as the high portion of QA at terminal count, for cascading stages.
16 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V 7
Input voltage VI 7 V 74LS160,74LS161,74LS163 7
Operating free-air temperature range 0 70 C DIP package 7
Storage temperature range Tstg -65 150 C 7
Supply voltage VCC 4.75 5 5.25 V 8
High-level output current IOH -400 μA 8
Low-level output current IOL 8 mA 8
Clock frequency fclock 0 25 MHz 8
Width of clock pulse tw (clock) 25 ns 8
Width of clear pulse tw (clear) 20 ns 8
Set up time, data inputs A,B,C,D tsu 20 ns 8
Hold time at any input th 3 ns 8
Operating free-air temperature TA 0 70 C 8
High-level input voltage VIH 2 V 8
Low-level input voltage VIL 0.8 V 8
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 8
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOH = −400 A 8
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 4 mA 8
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 8 mA 8
Input current at maximum input voltage, Data or ENP II 0.1 mA VCC = MAX, VI = 7 V 8
Input current at maximum input voltage, LOAD, CLK, or ENT II 0.2 mA VCC = MAX, VI = 7 V 8
High-level input current, Data or ENP IIH 20 A VCC = MAX, VI = 2.7 V 8
High-level input current, LOAD, CLK, or ENT IIH 40 A VCC = MAX, VI = 2.7 V 8
Low-level input current, Data or ENP IIL -0.4 mA VCC = MAX, VI = 0.4 V 8
Low-level input current, LOAD, CLK, or ENT IIL -0.8 mA VCC = MAX, VI = 0.4 V 8
Short-circuit output current IOS -20 -100 mA VCC = MAX 8
Supply current, all outputs high ICCH 18 31 mA VCC = MAX 8
Supply current, all outputs high ICCL 19 32 mA VCC = MAX 8
Maximum clock frequency fMAX 25 32 MHz VCC = 5 V, TA = 25°C 9
Propagation delay CLK to RCO, low-to-high tPLH 20 35 ns CL = 15 pF, RL = 2 k 9
Propagation delay CLK to RCO, high-to-low tPHL 18 35 ns CL = 15 pF, RL = 2 k 9
Propagation delay CLK to any Q (LOAD high), low-to-high tPLH 13 24 ns CL = 15 pF, RL = 2 k 9
Propagation delay CLK to any Q (LOAD high), high-to-low tPHL 18 27 ns CL = 15 pF, RL = 2 k 9
Propagation delay ENT to RCO, low-to-high tPLH 9 14 ns CL = 15 pF, RL = 2 k 9
Propagation delay ENT to RCO, high-to-low tPHL 9 14 ns CL = 15 pF, RL = 2 k 9
Propagation delay CLR to any Q, high-to-low tPHL 20 28 ns CL = 15 pF, RL = 2 k 9

CAD (KiCad official)

  • Symbol: XD74LS160
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd74ls160-etched.step / xd74ls160-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls160.step / xd74ls160.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (10 pp, sha256 1573a15dcc7949a4, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF