# XD74LS157

**XINLUDA** · Signal Switches, Multiplexers, Decoders · DIP-16

XD74LS157 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A/B | input | Select input that routes the A inputs to the outputs when low and the B inputs when high. |
| 2 | 1A | input | Data input A of gate 1, selected when A/B is low. |
| 3 | 1B | input | Data input B of gate 1, selected when A/B is high. |
| 4 | 1Y | output | Output of gate 1, which carries true data and is rated for IOL 8 mA and IOH -400 µA. |
| 5 | 2A | input | Data input A of gate 2, selected when A/B is low. |
| 6 | 2B | input | Data input B of gate 2, selected when A/B is high. |
| 7 | 2Y | output | Output of gate 2, which carries true data and is rated for IOL 8 mA and IOH -400 µA. |
| 8 | GND | power_in | Ground reference (0 V). |
| 9 | 3Y | output | Output of gate 3, which carries true data and is rated for IOL 8 mA and IOH -400 µA. |
| 10 | 3B | input | Data input B of gate 3, selected when A/B is high. |
| 11 | 3A | input | Data input A of gate 3, selected when A/B is low. |
| 12 | 4Y | output | Output of gate 4, which carries true data and is rated for IOL 8 mA and IOH -400 µA. |
| 13 | 4B | input | Data input B of gate 4, selected when A/B is high. |
| 14 | 4A | input | Data input A of gate 4, selected when A/B is low. |
| 15 | G | input | Strobe input, active low; when high it forces all four outputs low. |
| 16 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V |  | 5 |
| High-level output current | IOH |  |  | -400 | μA |  | 5 |
| Low-level output current | IOL |  |  | 8 | mA |  | 5 |
| Operating free-air temperature | TA | 0 |  | 70 | °C |  | 5 |
| High-level input voltage | VIH | 2 |  |  | V |  | 5 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 5 |
| Input clamp voltage | VIK |  |  | -1.5 | V | VCC = MIN, II = −18 mA | 5 |
| High-level output voltage | VOH | 2.7 | 3.4 |  | V | VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOH = −400 μA | 5 |
| Low-level output voltage | VOL |  | 0.25 | 0.4 | V | VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 4 mA | 5 |
| Low-level output voltage | VOL |  | 0.35 | 0.5 | V | VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 8 mA | 5 |
| Input current at maximum input voltage (A/B or G) | II |  |  | 0.2 | mA | VCC = MAX, VI = 7 V | 5 |
| Input current at maximum input voltage (A or B) | II |  |  | 0.1 | mA | VCC = MAX, VI = 7 V | 5 |
| High-level input current (A/B or G) | IIH |  |  | 40 | μA | VCC = MAX, VI = 2.7 V | 5 |
| High-level input current (A or B) | IIH |  |  | 20 | μA | VCC = MAX, VI = 2.7 V | 5 |
| Low-level input current (A/B or G) | IIL |  |  | -0.8 | mA | VCC = MAX, VI = 0.4 V | 5 |
| Low-level input current (A or B) | IIL |  |  | -0.4 | mA | VCC = MAX, VI = 0.4 V | 5 |
| Short-circuit output current | IOS | -20 |  | -100 | mA | VCC = MAX | 5 |
| Supply current | ICC |  | 9.7 | 16 | mA | VCC = MAX, Output open, All inputs at 4.5V | 5 |
| Supply voltage | VCC |  |  | 7 | V |  | 4 |
| Input voltage (74LS157) | VI |  |  | 7 | V |  | 4 |
| Operating free-air temperature range (DIP package) | TA | 0 |  | 70 | °C |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| Propagation delay, low-to-high-level output (Data to output) | tPLH |  | 9 | 14 | ns |  | 6 |
| Propagation delay, high-to-low-level output (Data to output) | tPHL |  | 9 | 14 | ns |  | 6 |
| Propagation delay, low-to-high-level output (Strobe G to output) | tPLH |  | 13 | 20 | ns | CL = 15 pF, RL = 2 k | 6 |
| Propagation delay, high-to-low-level output (Strobe G to output) | tPHL |  | 14 | 21 | ns | CL = 15 pF, RL = 2 k | 6 |
| Propagation delay, low-to-high-level output (Select A/B to output) | tPLH |  | 16 | 23 | ns |  | 6 |
| Propagation delay, high-to-low-level output (Select A/B to output) | tPHL |  | 18 | 27 | ns |  | 6 |

## CAD (KiCad official)

- Symbol: `XD74LS157`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `xd74ls157-etched.step` / `xd74ls157-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xd74ls157.step` / `xd74ls157.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588917722038620160) (8 pp, sha256 `13c66c29b4233e5b`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xd74ls157-datasheet.pdf)