# XD74LS145

**XINLUDA** · Signal Switches, Multiplexers, Decoders · DIP-16

XD74LS145 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 0 | output | Open-collector decimal output 0, low when BCD input is 0000, sinks up to 80 mA with 15 V breakdown. |
| 2 | 1 | output | Open-collector decimal output 1, low when BCD input is 0001, sinks up to 80 mA with 15 V breakdown. |
| 3 | 2 | output | Open-collector decimal output 2, low when BCD input is 0010, sinks up to 80 mA with 15 V breakdown. |
| 4 | 3 | output | Open-collector decimal output 3, low when BCD input is 0011, sinks up to 80 mA with 15 V breakdown. |
| 5 | 4 | output | Open-collector decimal output 4, low when BCD input is 0100, sinks up to 80 mA with 15 V breakdown. |
| 6 | 5 | output | Open-collector decimal output 5, low when BCD input is 0101, sinks up to 80 mA with 15 V breakdown. |
| 7 | 6 | output | Open-collector decimal output 6, low when BCD input is 0110, sinks up to 80 mA with 15 V breakdown. |
| 8 | GND | power_in | Ground terminal; all voltages are referenced to it. |
| 9 | 7 | output | Open-collector decimal output 7, low when BCD input is 0111, sinks up to 80 mA with 15 V breakdown. |
| 10 | 8 | output | Open-collector decimal output 8, low when BCD input is 1000, sinks up to 80 mA with 15 V breakdown. |
| 11 | 9 | output | Open-collector decimal output 9, low when BCD input is 1001, sinks up to 80 mA with 15 V breakdown. |
| 12 | D | input | BCD input D (most significant bit), one 74LS standard load, VIH min 2 V, VIL max 0.8 V. |
| 13 | C | input | BCD input C, one 74LS standard load, VIH min 2 V, VIL max 0.8 V. |
| 14 | B | input | BCD input B, one 74LS standard load, VIH min 2 V, VIL max 0.8 V. |
| 15 | A | input | BCD input A (least significant bit), one 74LS standard load, VIH min 2 V, VIL max 0.8 V. |
| 16 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.25 V (5 V nominal), absolute maximum 7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5 | 5.25 | V |  | 5 |
| Off-state output voltage | VO(off) |  |  | 15 | V |  | 5 |
| Operating free-air temperature | TA | -55 |  | 125 | C |  | 5 |
| Supply voltage | VCC |  |  | 7 | V | see Note 1 | 4 |
| Input voltage | VI |  |  | 7 | V | XD74LS145 | 4 |
| Operating free-air temperature range (DIP package) |  | 0 |  | 70 | C | DIP package | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | C |  | 4 |
| High-level input voltage | VIH | 2 |  |  | V |  | 5 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 5 |
| Input clamp voltage | VIK |  |  | -1.5 | V | VCC = MIN, II = −18 mA | 5 |
| Off-state output current | IO(off) |  |  | 250 | μA | VCC = MIN, VIL = 0.8 V, VIH = 2 V, VOH = 15 V | 5 |
| Output voltage (low-level, as labeled VO(on)) | VO(on) |  | 0.25 | 0.4 | V | VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 12 mA | 5 |
| Output voltage (low-level, as labeled VO(on)) | VO(on) |  | 0.35 | 0.5 | V | VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 24 mA | 5 |
| Output voltage (low-level, as labeled VO(on)) | VO(on) |  | 2.3 | 3 | V | VCC = MIN, VIH = 2 V, VIL = VIL MAX, IOL = 80 mA | 5 |
| Input current at maximum input voltage | II |  | 0.1 | 0.2 | mA | VCC = MAX, VI = 7 V | 5 |
| High-level input current | IIH |  | 20 | 40 | μA | VCC = MAX, VI = 2.7 V | 5 |
| Low-level input current | IIL |  | -0.4 | -0.8 | mA | VCC = MAX, VI = 0.4 V | 5 |
| Supply current | ICC |  | 7 | 13 | mA | VCC = MAX (See Note 2) | 5 |
| Propagation delay time, low-to-high-level output | tPLH |  |  | 50 | ns | VCC = 5 V, TA = 25°C, CL = 45 pF, RL = 665 Ω | 5 |
| Propagation delay time, high-to-high-level output | tPHL |  |  | 50 | ns | VCC = 5 V, TA = 25°C, CL = 45 pF, RL = 665 Ω | 5 |

## CAD (KiCad official)

- Symbol: `XD74LS145`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `xd74ls145-etched.step` / `xd74ls145-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xd74ls145.step` / `xd74ls145.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915166071435264) (6 pp, sha256 `c867d61a92cf4d55`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xd74ls145-datasheet.pdf)