component
XD74LS14
Public Made by Adomby adom
XINLUDA Inverters, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD74LS14
XINLUDA · Inverters · DIP-14
XD74LS14 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 Schmitt-trigger inverter input, with separate positive-going (VT+) and negative-going (VT-) thresholds for noise immunity. |
| 2 | 1Y | output | Channel 1 inverter output, Y = NOT A. |
| 3 | 2A | input | Channel 2 Schmitt-trigger inverter input, with separate positive-going (VT+) and negative-going (VT-) thresholds for noise immunity. |
| 4 | 2Y | output | Channel 2 inverter output, Y = NOT A. |
| 5 | 3A | input | Channel 3 Schmitt-trigger inverter input, with separate positive-going (VT+) and negative-going (VT-) thresholds for noise immunity. |
| 6 | 3Y | output | Channel 3 inverter output, Y = NOT A. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 4Y | output | Channel 4 inverter output, Y = NOT A. |
| 9 | 4A | input | Channel 4 Schmitt-trigger inverter input, with separate positive-going (VT+) and negative-going (VT-) thresholds for noise immunity. |
| 10 | 5Y | output | Channel 5 inverter output, Y = NOT A. |
| 11 | 5A | input | Channel 5 Schmitt-trigger inverter input, with separate positive-going (VT+) and negative-going (VT-) thresholds for noise immunity. |
| 12 | 6Y | output | Channel 6 inverter output, Y = NOT A. |
| 13 | 6A | input | Channel 6 Schmitt-trigger inverter input, with separate positive-going (VT+) and negative-going (VT-) thresholds for noise immunity. |
| 14 | VCC | power_in | Power supply; recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum supply voltage 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V | 3 | |
| High-level output current | IOH | -0.4 | mA | 3 | |||
| Low-level output current | IOL | 8 | mA | 3 | |||
| Operating free-air temperature | TA | 0 | 70 | °C | 3 | ||
| Supply voltage | VCC | 7 | V | 3 | |||
| Input voltage | 7 | V | 3 | ||||
| Junction temperature | TJ | 150 | °C | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Positive-going threshold voltage | VT+ | 1.4 | 1.6 | 1.9 | V | VCC = 5 V | 4 |
| Negative-going threshold voltage | VT- | 0.5 | 0.8 | 1 | V | VCC = 5 V | 4 |
| Hysteresis (VT+, VT-) | VT+, VT- | 0.4 | 0.8 | V | VCC = 5 V | 4 | |
| Input clamp voltage | VIK | -1.5 | V | VCC = MIN, II = -18 mA | 4 | ||
| High-level output voltage | VOH | 2.4 | 3.4 | V | VCC = MIN, VI = 0.5 V, IOH = -0.4 mA | 4 | |
| Low-level output voltage | VOL | 0.25 | 0.4 | V | VCC = MIN, VI = 1.9 V, IOL = 4 mA | 4 | |
| Low-level output voltage | VOL | 0.35 | 0.5 | V | VCC = MIN, VI = 1.9 V, IOL = 8 mA | 4 | |
| Positive-going input current | IT+ | 0.14 | mA | VCC = 5 V, VI = VT+ | 4 | ||
| Negative-going input current | IT- | 0.18 | mA | VCC = 5 V, VI = VT- | 4 | ||
| Input current at maximum input voltage | II | 0.1 | mA | VCC = MAX, VI = 7 V | 4 | ||
| High-level input current | IIH | 20 | µA | VCC = MAX, VIH = 2.7 V | 4 | ||
| Low-level input current | IIL | -0.4 | mA | VCC = MAX, VIL = 0.4 V | 4 | ||
| Short-circuit output current | IOS | -20 | -100 | mA | VCC = MAX | 4 | |
| Supply current, outputs high | ICCH | 8.6 | 16 | mA | VCC = MAX | 4 | |
| Supply current, outputs low | ICCL | 12 | 21 | mA | VCC = MAX | 4 | |
| Propagation delay time, low-to-high-level output | tPLH | 15 | 22 | ns | RL = 400 Ω and CL = 15 pF, or RL = 2 kΩ and CL = 15 pF | 4 | |
| Propagation delay time, high-to-low-level output | tPHL | 15 | 22 | ns | RL = 400 Ω and CL = 15 pF, or RL = 2 kΩ and CL = 15 pF | 4 | |
| Junction-to-ambient thermal resistance | RθJA | 54.9 | °C/W | 3 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 42.5 | °C/W | 3 | |||
| Junction-to-board thermal resistance | RθJB | 34.7 | °C/W | 3 | |||
| Junction-to-top characterization parameter | ψJT | 27.8 | °C/W | 3 | |||
| Junction-to-board characterization parameter | ψJB | 34.6 | °C/W | 3 |
CAD (KiCad official)
- Symbol:
XD74LS14 - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
xd74ls14-etched.step/xd74ls14-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd74ls14.step/xd74ls14.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (14 pp, sha256
b83eb03fc7a65d62, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).