# XD74LS112

**XINLUDA** · Flip Flops · DIP-16

XD74LS112 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLK | input | Clock input of flip-flop 1, triggered on the negative-going edge. |
| 2 | 1K | input | K data input of flip-flop 1. |
| 3 | 1J | input | J data input of flip-flop 1. |
| 4 | 1PRE | input | Active-low preset input of flip-flop 1 that sets the outputs regardless of the other inputs. |
| 5 | 1Q | output | True output of flip-flop 1. |
| 6 | 1Q̅ | output | Complementary output of flip-flop 1. |
| 7 | 2Q̅ | output | Complementary output of flip-flop 2. |
| 8 | GND | power_in | Ground terminal, the reference for all voltage values. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2PRE | input | Active-low preset input of flip-flop 2 that sets the outputs regardless of the other inputs. |
| 11 | 2J | input | J data input of flip-flop 2. |
| 12 | 2K | input | K data input of flip-flop 2. |
| 13 | 2CLK | input | Clock input of flip-flop 2, triggered on the negative-going edge. |
| 14 | 2CLR | input | Active-low clear input of flip-flop 2 that resets the outputs regardless of the other inputs. |
| 15 | 1CLR | input | Active-low clear input of flip-flop 1 that resets the outputs regardless of the other inputs. |
| 16 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V with an absolute maximum of 7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V |  | 4 |
| High-level input voltage | VIH | 2 |  |  | V |  | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 4 |
| High-level output current | IOH |  |  | -0.4 | mA |  | 4 |
| Low-level output current | IOL |  |  | 8 | mA |  | 4 |
| Clock frequency | fclock | 0 |  | 30 | MHz |  | 4 |
| Pulse duration, CLK high | tw | 20 |  |  | ns | CLK high | 4 |
| Pulse duration, PRE or CLR low | tw | 25 |  |  | ns | PRE or CLR low | 4 |
| Setup time, data high or low before CLK↓ | tsu | 20 |  |  | ns | Data high or low | 4 |
| Setup time, CLR inactive before CLK↓ | tsu | 25 |  |  | ns | CLR inactive | 4 |
| Setup time, PRE inactive before CLK↓ | tsu | 20 |  |  | ns | PRE inactive | 4 |
| Hold time, data after CLK↓ | th | 0 |  |  | ns |  | 4 |
| Operating free-air temperature | TA | 0 |  | 70 | C |  | 4 |
| Supply voltage | VCC |  |  | 7 | V | See Note 1 (with respect to network ground) | 3 |
| Input voltage, 74LS112 | VI |  |  | 7 | V |  | 3 |
| Operating free-air temperature range, DIP package | TA | 0 |  | 70 | C |  | 3 |
| Storage temperature range | Tstg | -65 |  | 150 | C |  | 3 |
| Input clamp voltage | VIK |  |  | -1.5 | V | VCC = MIN, II = −18 mA | 4 |
| High-level output voltage | VOH | 2.7 | 3.4 |  | V | VCC = MIN, VIH = 2 V, IOH = −0.4 mA, VIL = MAX | 4 |
| Low-level output voltage (row 1) | VOL |  | 0.25 | 0.4 | V | VCC = MIN, VIH = 2 V, VIL = MAX, IOL = 8 mA | 4 |
| Low-level output voltage (row 2) | VOL |  | 0.35 | 0.5 | V | VCC = MIN, VIH = 2 V, VIL = MAX, IOL = 8 mA | 4 |
| Input current at maximum input voltage, J or K | II |  |  | 0.1 | mA | J or K; VCC = MAX, VI = 7 V | 4 |
| Input current at maximum input voltage, CLR or PRE (row 1) | II |  |  | 0.3 | mA | CLR or PRE; VCC = MAX, VI = 7 V | 4 |
| Input current at maximum input voltage, CLR or PRE (row 2) | II |  |  | 0.4 | mA | CLR or PRE; VCC = MAX, VI = 7 V | 4 |
| High-level input current, J or K | IIH |  |  | 20 | μA | J or K; VCC = MAX, VI = 2.7 V | 4 |
| High-level input current, CLR or PRE (row 1) | IIH |  |  | 60 | μA | CLR or PRE; VCC = MAX, VI = 2.7 V | 4 |
| High-level input current, CLR or PRE (row 2) | IIH |  |  | 80 | μA | CLR or PRE; VCC = MAX, VI = 2.7 V | 4 |
| Low-level input current, J or K | IIL |  |  | -0.4 | mA | J or K; VCC = MAX, VI = 0.4 V | 4 |
| Low-level input current, CLR or PRE | IIL |  |  | -0.8 | mA | CLR or PRE; VCC = MAX, VI = 0.4 V | 4 |
| Short-circuit output current | IOS | -20 |  | -100 | mA | VCC = MAX, see Note 2 | 4 |
| Supply current (total) | ICC |  | 4 | 6 | mA | VCC = MAX, see Note 3 | 4 |

## CAD (KiCad official)

- Symbol: `XD74LS112`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `xd74ls112-etched.step` / `xd74ls112-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xd74ls112.step` / `xd74ls112.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588916374327971840) (5 pp, sha256 `d415f069cf3f6235`, retrieved 2026-10-15, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xd74ls112-datasheet.pdf)