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Contents

README

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XD74LS11

XINLUDA · Gates · DIP-14

XD74LS11 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
2 1B input Gate 1 input B; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
3 2A input Gate 2 input A; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
4 2B input Gate 2 input B; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
5 2C input Gate 2 input C; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
6 2Y output Gate 2 AND output, rated for IOH of −0.4 mA and IOL of 8 mA.
7 GND power_in Ground, the 0 V supply reference.
8 3Y output Gate 3 AND output, rated for IOH of −0.4 mA and IOL of 8 mA.
9 3A input Gate 3 input A; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
10 3B input Gate 3 input B; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
11 3C input Gate 3 input C; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
12 1Y output Gate 1 AND output, rated for IOH of −0.4 mA and IOL of 8 mA.
13 1C input Gate 1 input C; the gate output is high only when A, B and C are all high (VIH min 2 V, VIL max 0.8 V).
14 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (nominal 5 V), absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
High-level output current IOH -0.4 mA 3
Low-level output current IOL 8 mA 3
Operating free-air temperature TA 0 70 C 3
Supply voltage VCC 7 V see Note 1 2
Input voltage VI 7 V 74LS11 2
Operating free-air temperature range 0 70 C DIP package 2
Storage temperature range Tstg -65 150 C 2
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 3
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = MAX, IOH = −0.4 mA 3
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, IOL = 4 mA 3
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, IOL = 8 mA 3
Input current at maximum input voltage II 0.1 mA VCC = MAX, VI = 7 V 3
High-level input current IIH 20 µA VCC = MAX, VI = 2.7 V 3
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 3
Short-circuit output current IOS -20 -100 mA VCC = MAX 3
Supply current, outputs high ICCH 1.8 3.6 mA VCC = MAX, VI = 4.5 V 3
Supply current, outputs low ICCL 3.3 6.6 mA VCC = MAX, VI = 0 V 3
Propagation delay time, A, B or C to Y tPHL 10 20 ns RL = 2 kΩ, CL = 15 pF, VCC = 5 V, TA = 25 C 3

CAD (KiCad official)

  • Symbol: XD74LS11
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls11-etched.step / xd74ls11-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls11.step / xd74ls11.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 79df2b02c1d79fb1, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF