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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	7d ago
viewers	xd74ls08: viewers · Ray	7d ago
package.json	Publish 0.1.0 · Ray	7d ago
page.json	Set visibility: public · Ray	7d ago
README.md	Publish 0.1.0 · Ray	7d ago
xd74ls08-etched.glb	Publish 0.1.0 · Ray	7d ago
xd74ls08-etched.step	xd74ls08: factory component page (tier=lcsc) · Ray	7d ago
xd74ls08-hero.glb	xd74ls08: hero GLB from the etched model (keeps the MPN mark) · Ray	7d ago
xd74ls08-hero.overlay.json	Publish 0.1.0 · Ray	7d ago
xd74ls08.glb	Publish 0.1.0 · Ray	7d ago
xd74ls08.kicad_mod	Publish 0.1.0 · Ray	7d ago
xd74ls08.kicad_sym	Publish 0.1.0 · Ray	7d ago
xd74ls08.lbr	Publish 0.1.0 · Ray	7d ago
xd74ls08.step	Publish 0.1.0 · Ray	7d ago

XD74LS08

XINLUDA · Logic Gates · DIP-14

XD74LS08 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Gate 1 input A.
2	1B	input	Gate 1 input B.
3	1Y	output	Gate 1 output, high only when 1A and 1B are both high.
4	2A	input	Gate 2 input A.
5	2B	input	Gate 2 input B.
6	2Y	output	Gate 2 output, high only when 2A and 2B are both high.
7	GND	power_in	Ground.
8	3Y	output	Gate 3 output, high only when 3A and 3B are both high.
9	3A	input	Gate 3 input A.
10	3B	input	Gate 3 input B.
11	4Y	output	Gate 4 output, high only when 4A and 4B are both high.
12	4A	input	Gate 4 input A.
13	4B	input	Gate 4 input B.
14	VCC	power_in	Supply voltage, recommended 4.75 V to 5.25 V (nominal 5 V), absolute maximum 7 V.

Key specifications

Parameter	Value
Manufacturer	XINLUDA
Package	DIP-14
Category	Logic
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	4.75	5	5.25	V		3
High-level input voltage	VIH	2			V		3
Low-level input voltage	VIL			0.8	V		3
High-level output current	IOH			-0.4	mA		3
Low-level output current	IOL			8	mA		3
Operating free-air temperature	TA	0		70	°C		3
Supply voltage	VCC			7	V	see Note 1	2
Input voltage (74LS08)	VI			7	V		2
Storage temperature range	Tstg	-65		150	°C		2
Input clamp voltage	VIK			-1.5	V	VCC = MIN, II = -18 mA	3
High-level output voltage	VOH	2.7	3.4		V	VCC = MIN, VIL = MAX, IOH = -0.4 mA	3
Low-level output voltage	VOL		0.25	0.4	V	VCC = MIN, VIH = 2 V, IOL = 4 mA	3
Low-level output voltage	VOL		0.35	0.5	V	VCC = MIN, VIH = 2 V, IOL = 8 mA	3
Input current at maximum input voltage	II			0.1	mA	VCC = MAX, VI = 7 V	3
High-level input current	IIH			20	µA	VCC = MAX, VI = 2.7 V	3
Low-level input current	IIL			-0.4	mA	VCC = MAX, VI = 0.4 V	3
Short-circuit output current	IOS	-20		-100	mA	VCC = MAX	3
Supply current, outputs high	ICCH		2.4	4.8	mA	VCC = MAX, VI = 4.5 V	3
Supply current, outputs low	ICCL		4.4	8.8	mA	VCC = MAX, VI = 0 V	3
Propagation delay time, high-to-low level output	tPHL		10	20	ns	VCC = 5 V, TA = 25 C, RL = 2 kΩ, CL = 15 pF (A or B to Y)	3
Thermal resistance, DIP package			96		°C/W		2

CAD (KiCad official)

Symbol: XD74LS08
Footprint: Package_DIP:DIP-14_W7.62mm
3D model: DIP-14 (KiCad packages3D, STEP)
3D model files: xd74ls08-etched.step / xd74ls08-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls08.step / xd74ls08.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XINLUDA datasheet (5 pp, sha256 e46ba5a1c45d414d, retrieved 2026-10-16, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF