# XD74LS07

**XINLUDA** · Buffers / Drivers · PDIP-14

XD74LS07 from XINLUDA, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input 1 of buffer gate 1; unused inputs must be held at VCC or GND. |
| 2 | 1Y | output | Open-collector output 1, rated to 30 V off-state and sinks up to 40 mA. |
| 3 | 2A | input | Input 2 of buffer gate 2; unused inputs must be held at VCC or GND. |
| 4 | 2Y | output | Open-collector output 2, rated to 30 V off-state and sinks up to 40 mA. |
| 5 | 3A | input | Input 3 of buffer gate 3; unused inputs must be held at VCC or GND. |
| 6 | 3Y | output | Open-collector output 3, rated to 30 V off-state and sinks up to 40 mA. |
| 7 | GND | power_in | Ground pin. |
| 8 | 4Y | output | Open-collector output 4, rated to 30 V off-state and sinks up to 40 mA. |
| 9 | 4A | input | Input 4 of buffer gate 4; unused inputs must be held at VCC or GND. |
| 10 | 5Y | output | Open-collector output 5, rated to 30 V off-state and sinks up to 40 mA. |
| 11 | 5A | input | Input 5 of buffer gate 5; unused inputs must be held at VCC or GND. |
| 12 | 6Y | output | Open-collector output 6, rated to 30 V off-state and sinks up to 40 mA. |
| 13 | 6A | input | Input 6 of buffer gate 6; unused inputs must be held at VCC or GND. |
| 14 | VCC | power_in | Power pin; recommended supply 4.75 V to 5.25 V (5 V nominal), absolute max 7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | PDIP-14 |
| Category | Logic ICs |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC |  |  | 7 | V |  | 3 |
| Input voltage | VI |  |  | 7 | V |  | 3 |
| Output voltage | VO |  |  | 30 | V | off state | 3 |
| Operating virtual junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| Junction-to-ambient thermal resistance | RθJA |  | 50.2 |  | °C/W | DIP 14 pins | 3 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 37.5 |  | °C/W | DIP 14 pins | 3 |
| Junction-to-board thermal resistance | RθJB |  | 30 |  | °C/W | DIP 14 pins | 3 |
| Junction-to-top characterization parameter | ψJT |  | 22.3 |  | °C/W | DIP 14 pins | 3 |
| Junction-to-board characterization parameter | ψJB |  | 29.9 |  | °C/W | DIP 14 pins | 3 |
| ESD HBM | V(ESD) | -2000 |  | 2000 | V | Human-body model, ANSI/ESDA/JEDEC JS-001 | 3 |
| ESD CDM | V(ESD) | -1000 |  | 1000 | V | Charged-device model, JESD22-C101 | 3 |
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V |  | 4 |
| High-level input voltage | VIH | 2 |  |  | V |  | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 4 |
| High-level output voltage | VOH |  |  | 30 | V |  | 4 |
| Low-level output current | IOL |  |  | 40 | mA |  | 4 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 4 |
| Input clamp voltage | VIK |  |  | -1.5 | V | VCC = MIN, II = -12 mA | 4 |
| High-level output current | IOH |  |  | 0.25 | mA | VCC = MIN, VIH = 2 V, VOH = 30 V | 4 |
| Low-level output voltage | VOL |  |  | 0.4 | V | VCC = MIN, VIL = 0.8 V, IOL = 16 mA | 4 |
| Low-level output voltage | VOL |  |  | 0.7 | V | VCC = MIN, VIL = 0.8 V, IOL = MAX (40 mA) | 4 |
| Input current at max input voltage | II |  |  | 1 | mA | VCC = MAX, VI = 7 V | 4 |
| High-level input current | IIH |  |  | 20 | µA | VCC = MAX, VI = 2.4 V | 4 |
| Low-level input current | IIL |  |  | -0.2 | mA | VCC = MAX, VI = 0.4 V | 4 |
| Supply current, outputs high | ICCH |  |  | 14 | mA | VCC = MAX | 4 |
| Supply current, outputs low | ICCL |  |  | 45 | mA | VCC = MAX | 4 |
| Propagation delay, low-to-high | tPLH |  | 6 | 10 | ns | VCC = 5 V, TA = 25°C, RL = 110 Ω, CL = 15 pF, A to Y | 4 |
| Propagation delay, high-to-low | tPHL |  | 19 | 30 | ns | VCC = 5 V, TA = 25°C, RL = 110 Ω, CL = 15 pF, A to Y | 4 |

## CAD (KiCad official)

- Symbol: `XD74LS07`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `xd74ls07-etched.step` / `xd74ls07-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xd74ls07.step` / `xd74ls07.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XINLUDA datasheet](docs/xd74ls07-datasheet.pdf) (11 pp, sha256 `0345d20c44e64221`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xd74ls07-datasheet.pdf)