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XD74LS06
Public Made by Adomby adom
XINLUDA Buffers, Drivers, Receivers, Transceivers, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD74LS06
XINLUDA · Buffers, Drivers, Receivers, Transceivers · PDIP-14
XD74LS06 from XINLUDA, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input of inverter gate 1; inputs are diode-clamped and overvoltage tolerant up to 5.5 V at any valid VCC. |
| 2 | 1Y | output | Open-collector output of inverter gate 1; it can be pulled up to 30 V and sinks up to 30 mA for the XD74LS06. |
| 3 | 2A | input | Input of inverter gate 2; inputs are diode-clamped and overvoltage tolerant up to 5.5 V at any valid VCC. |
| 4 | 2Y | output | Open-collector output of inverter gate 2; it can be pulled up to 30 V and sinks up to 30 mA for the XD74LS06. |
| 5 | 3A | input | Input of inverter gate 3; inputs are diode-clamped and overvoltage tolerant up to 5.5 V at any valid VCC. |
| 6 | 3Y | output | Open-collector output of inverter gate 3; it can be pulled up to 30 V and sinks up to 30 mA for the XD74LS06. |
| 7 | GND | power_in | Ground reference for all voltages on the device. |
| 8 | 4Y | output | Open-collector output of inverter gate 4; it can be pulled up to 30 V and sinks up to 30 mA for the XD74LS06. |
| 9 | 4A | input | Input of inverter gate 4; inputs are diode-clamped and overvoltage tolerant up to 5.5 V at any valid VCC. |
| 10 | 5Y | output | Open-collector output of inverter gate 5; it can be pulled up to 30 V and sinks up to 30 mA for the XD74LS06. |
| 11 | 5A | input | Input of inverter gate 5; inputs are diode-clamped and overvoltage tolerant up to 5.5 V at any valid VCC. |
| 12 | 6Y | output | Open-collector output of inverter gate 6; it can be pulled up to 30 V and sinks up to 30 mA for the XD74LS06. |
| 13 | 6A | input | Input of inverter gate 6; inputs are diode-clamped and overvoltage tolerant up to 5.5 V at any valid VCC. |
| 14 | VCC | power_in | Supply voltage of 4.5 V to 5.5 V (5 V nominal) with a local 0.1 µF bypass capacitor recommended close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| High-level input voltage | VIH | 2 | V | 4 | |||
| Low-level input voltage | VIL | 0.8 | V | 4 | |||
| High-level output voltage (XL/XD74LS06) | VOH | 30 | V | 4 | |||
| Low-level output current (XD74LS06) | IOL | 30 | mA | 4 | |||
| Operating free-air temperature (XD74LS06) | TA | -40 | 85 | °C | 4 | ||
| Supply voltage | VCC | 7 | V | 4 | |||
| Input voltage | VI | 7 | V | 4 | |||
| Output voltage (XL/XD74LS06) | VO | 30 | V | Output in off state (note 3) | 4 | ||
| Absolute maximum junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Electrostatic discharge, human-body model | V(ESD) | -500 | 500 | V | HBM, per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Electrostatic discharge, charged-device model | V(ESD) | -2000 | 2000 | V | CDM, per JEDEC JESD22-C101 | 4 | |
| Input clamp voltage | VIK | -1.5 | V | VCC = MIN, II = -12 mA | 5 | ||
| High-level output current | IOH | 0.25 | mA | VCC = MIN, VIL = 0.8 V, VOH = 30 V, XL/XD74LS06 | 5 | ||
| Low-level output voltage | VOL | 0.25 | 0.4 | V | VCC = MIN, VIH = 2 V, IOL = 16 mA | 5 | |
| Low-level output voltage | VOL | 0.7 | V | VCC = MIN, VIH = 2 V, IOL = 30 mA | 5 | ||
| Input current at maximum input voltage | II | 1 | mA | VCC = MAX, VI = 7 V | 5 | ||
| High-level input current | IIH | 20 | µA | VCC = MAX, VI = 2.4 V | 5 | ||
| Low-level input current | IIL | -0.2 | mA | VCC = MAX, VI = 0.4 V | 5 | ||
| Supply current, outputs high | ICCH | 18 | mA | VCC = MAX | 5 | ||
| Supply current, outputs low | ICCL | 60 | mA | VCC = MAX | 5 | ||
| Propagation delay low-to-high (A to Y) | tPLH | 7 | 15 | ns | VCC = 5 V, TA = 25°C, RL = 110 Ω, CL = 15 pF | 5 | |
| Propagation delay high-to-low (A to Y) | tPHL | 10 | 20 | ns | VCC = 5 V, TA = 25°C, RL = 110 Ω, CL = 15 pF | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 50.2 | °C/W | DIP 14 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 37.5 | °C/W | DIP 14 pins | 4 | ||
| Junction-to-board thermal resistance | RθJB | 30 | °C/W | DIP 14 pins | 4 | ||
| Junction-to-top characterization parameter | ψJT | 22.3 | °C/W | DIP 14 pins | 4 | ||
| Junction-to-board characterization parameter | ψJB | 29.9 | °C/W | DIP 14 pins | 4 |
CAD (KiCad official)
- Symbol:
XD74LS06 - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
xd74ls06-etched.step/xd74ls06-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd74ls06.step/xd74ls06.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (11 pp, sha256
5f9724c5f8180c69, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).