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XD74C922

Public Made by Adom

by adom

XINLUDA Signal Switches, Multiplexers, Decoders, DIP-18. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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XD74C922

XINLUDA · Signal Switches, Multiplexers, Decoders · DIP-18

XD74C922 from XINLUDA, in a DIP-18. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ROW Y1 input Row 1 input from the key matrix with an on-chip pull-up; goes low when a key in row Y1 is closed during column scan.
2 ROW Y2 input Row 2 input from the key matrix with an on-chip pull-up; goes low when a key in row Y2 is closed during column scan.
3 ROW Y3 input Row 3 input from the key matrix with an on-chip pull-up; goes low when a key in row Y3 is closed during column scan.
4 ROW Y4 input Row 4 input from the key matrix with an on-chip pull-up; goes low when a key in row Y4 is closed during column scan.
5 OSCILLATOR input Schmitt-trigger oscillator input that sets the keyboard scan rate, driven by an external capacitor or external clock.
6 KEYBOUNCE MASK input Key bounce mask input; a single external capacitor sets the debounce period, and omitting the capacitor defeats debounce.
7 COLUMN X4 output Column 4 open-drain scan output to the key matrix, driven low sequentially (column ON resistance max 1400 ohm at VCC=5V).
8 COLUMN X3 output Column 3 open-drain scan output to the key matrix, driven low sequentially (column ON resistance max 1400 ohm at VCC=5V).
9 GND power_in Ground.
10 COLUMN X2 output Column 2 open-drain scan output to the key matrix, driven low sequentially (column ON resistance max 1400 ohm at VCC=5V).
11 COLUMN X1 output Column 1 open-drain scan output to the key matrix, driven low sequentially (column ON resistance max 1400 ohm at VCC=5V).
12 DATA AVAILABLE output Goes high when a valid keyboard entry has been made and returns low when the key is released.
13 OUTPUT ENABLE input Active-low output enable; taking it low enables the 3-STATE data outputs.
14 DATA OUT D tri_state 3-STATE LPTTL-compatible encoded key output bit D, holding the last key pressed.
15 DATA OUT C tri_state 3-STATE LPTTL-compatible encoded key output bit C, holding the last key pressed.
16 DATA OUT B tri_state 3-STATE LPTTL-compatible encoded key output bit B, holding the last key pressed.
17 DATA OUT A tri_state 3-STATE LPTTL-compatible encoded key output bit A, holding the last key pressed.
18 VCC power_in Positive supply, operating range 3V to 15V (absolute maximum 18V).

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-18
Category Logic
Pins 18

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating VCC Range VCC 3 15 V 4
Operating Temperature Range -40 85 °C 4
Supply voltage VCC (absolute maximum) VCC 18 V 4
Storage Temperature Range -65 150 °C 4
Lead Temperature 260 °C Soldering, 10 seconds 4
Power Dissipation (PD), Dual-In-Line PD 700 mW Dual-In-Line package 4
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 3 3.6 4.3 V VCC = 5V, IIN = 0.7 mA 4
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 6 6.8 8.6 V VCC = 10V, IIN = 1.4 mA 4
Positive-Going Threshold Voltage at Osc and KBM Inputs VT 9 10 12.9 V VCC = 15V, IIN = 2.1 mA 4
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 0.7 1.4 2 V VCC = 5V, IIN = 0.7 mA 4
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 1.4 3.2 4 V VCC = 10V, IIN = 1.4 mA 4
Negative-Going Threshold Voltage at Osc and KBM Inputs VT 2.1 5 6 V VCC = 15V, IIN = 2.1 mA 4
Logical '1' Input Voltage, Except Osc and KBM Inputs VIN(1) 3.5 4.5 V VCC = 5V 4
Logical '1' Input Voltage, Except Osc and KBM Inputs VIN(1) 8 9 V VCC = 10V 4
Logical '1' Input Voltage, Except Osc and KBM Inputs VIN(1) 12.5 13.5 V VCC = 15V 4
Logical '0' Input Voltage, Except Osc and KBM Inputs VIN(0) 0.5 1.5 V VCC = 5V 4
Logical '0' Input Voltage, Except Osc and KBM Inputs VIN(0) 1 2 V VCC = 10V 4
Logical '0' Input Voltage, Except Osc and KBM Inputs VIN(0) 1.5 2.5 V VCC = 15V 4
Row Pull-Up Current at Y1, Y2, Y3, Y4 and Y5 Inputs Irp 2 10 22 µA VCC = 5V, VIN = 0.1 VCC 4
Logical '1' Output Voltage VOUT(1) 4.5 V VCC = 5V, IO = 10 µA 4
Logical '1' Output Voltage VOUT(1) 9 V VCC = 10V, IO = 10 µA 4
Logical '1' Output Voltage VOUT(1) 13.5 V VCC = 15V, IO = 10 µA 4
Logical '0' Output Voltage VOUT(0) 0.5 V VCC = 5V, IO = 10 µA 4
Logical '0' Output Voltage VOUT(0) 1 V VCC = 10V, IO = 10 µA 4
Logical '0' Output Voltage VOUT(0) 1.5 V VCC = 15V, IO = 10 µA 4
Column 'ON' Resistance at X1, X2, X3 and X4 Outputs Ron 500 1400 Ω VCC = 5V, VO = 0.5V 4
Column 'ON' Resistance at X1, X2, X3 and X4 Outputs Ron 300 700 Ω VCC = 10V, VO = 1V 4
Column 'ON' Resistance at X1, X2, X3 and X4 Outputs Ron 200 500 Ω VCC = 15V, VO = 1.5V 4
Supply Current ICC 0.55 1.1 mA Osc at 0V, one Y low; VCC = 5V 4
Supply Current ICC 1.1 1.9 mA Osc at 0V, one Y low; VCC = 10V 4
Supply Current ICC 1.7 2.6 mA Osc at 0V, one Y low; VCC = 15V 4
Logical '1' Input Current at Output Enable IIN(1) 0.005 1 µA VCC = 15V, VIN = 15V 4
Logical '0' Input Current at Output Enable IIN(0) 0.005 1 µA VCC = 15V, VIN = 0V 4
Logical '0' Input Voltage, Except Osc and KBM Inputs (CMOS/LPTTL) VIN(0) 0.8 V VCC = 4.75V 4
Logical '1' Output Voltage (CMOS/LPTTL) VOUT(1) 2.4 V VCC = 4.75V, IO = 360 µA 4
Logical '0' Output Voltage (CMOS/LPTTL) VOUT(0) 0.4 V VCC = 4.75V, IO = 360 µA 5
Output Source Current (P-Channel) ISOURCE 1.75 3.3 mA VCC = 5V, VOUT = 0V, TA = 25°C 5
Output Source Current (P-Channel) ISOURCE 8 15 mA VCC = 10V, VOUT = 0V, TA = 25°C 5
Output Sink Current (N-Channel) ISINK 1.75 3.6 mA VCC = 5V, VOUT = VCC, TA = 25°C 5
Output Sink Current (N-Channel) ISINK 8 16 mA VCC = 10V, VOUT = VCC, TA = 25°C 5
Propagation Delay Time to Logical '0' or Logical '1' from D.A. tpd0, tpd1 60 150 ns CL = 50 pF (Figure 1), VCC = 5V 5
Propagation Delay Time to Logical '0' or Logical '1' from D.A. tpd0, tpd1 35 80 ns CL = 50 pF (Figure 1), VCC = 10V 5
Propagation Delay Time to Logical '0' or Logical '1' from D.A. tpd0, tpd1 25 60 ns CL = 50 pF (Figure 1), VCC = 15V 5
Propagation Delay Time from Logical '0' or '1' into High Impedance State t0H, t1H 80 200 ns RL = 10k, CL = 10 pF (Figure 2), VCC = 5V, RL = 10k 5
Propagation Delay Time from Logical '0' or '1' into High Impedance State t0H, t1H 65 150 ns RL = 10k (Figure 2), VCC = 10V, CL = 10 pF 5
Propagation Delay Time from Logical '0' or '1' into High Impedance State t0H, t1H 50 110 ns RL = 10k, CL = 10 pF (Figure 2), VCC = 15V 5
Propagation Delay Time from High Impedance State to Logical '0' or '1' tH0, tH1 100 250 ns RL = 10k, CL = 50 pF (Figure 2), VCC = 5V, RL = 10k 5
Propagation Delay Time from High Impedance State to Logical '0' or '1' tH0, tH1 55 125 ns RL = 10k, CL = 50 pF (Figure 2), VCC = 10V, CL = 50 pF 5
Propagation Delay Time from High Impedance State to Logical '0' or '1' tH0, tH1 40 90 ns RL = 10k, CL = 50 pF (Figure 2), VCC = 15V 5
Input Capacitance CIN 5 7.5 pF Any input (Note 4) 5
3-STATE Output Capacitance COUT 10 pF Any output (Note 4) 5

CAD (KiCad official)

  • Symbol: XD74C922
  • Footprint: Package_DIP:DIP-18_W7.62mm
  • 3D model: DIP-18 (KiCad packages3D, STEP)
  • 3D model files: xd74c922-etched.step / xd74c922-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74c922.step / xd74c922.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (11 pp, sha256 5a5db127be601c00, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF