component
XD551
Public Made by Adomby adom
XINLUDA Timers / Counters, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD551
XINLUDA · Timers / Counters · DIP-8
XD551 from XINLUDA, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference for the timer; a low-impedance path is provided between DISCH and GND whenever the output is low. |
| 2 | TRIG | input | Start-of-timing input; when TRIG is below 1/2 CONT the output is set high and the discharge is open. |
| 3 | OUT | output | High-current timer output signal, rated to sink 100 mA (max) and source 10 mA (typ). |
| 4 | RESET | input | Active-low reset input that forces the output and discharge low and can override all other inputs. |
| 5 | CONT | input | Controls the comparator thresholds, setting them at 2/3 VDD, and allows a bypass capacitor connection. |
| 6 | THRES | input | End-of-timing input; when THRES is above CONT the output is set low and the discharge is low. |
| 7 | DISCH | output | Open-collector output used to discharge the timing capacitor. |
| 8 | VDD | power_in | Power-supply voltage input; the recommended supply range is 2 V to 15 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-8 |
| Category | Clock/Timing |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, VDD (recommended) | VDD | 2 | 15 | V | 4 | ||
| Operating free-air temperature range, TA (recommended) | TA | 0 | 70 | °C | 4 | ||
| Supply voltage, VDD (absolute maximum) | VDD | 17.5 | V | Note 1: all voltages with respect to network GND | 4 | ||
| Input voltage range, any input | VI | -0.3 | V | any input; upper limit printed as VDD | 4 | ||
| Sink current, discharge or output | 100 | mA | 4 | ||||
| Source current, output | IO | 10 | mA | 4 | |||
| Storage temperature range | -50 | 150 | °C | 4 | |||
| Lead temperature | 260 | °C | 1.6 mm (1/16 inch) from case for 10 seconds | 4 | |||
| Power rating, DIP8 package | 1000 | mW | DIP8, TA ≤ 25°C | 4 | |||
| Derating factor, DIP8 package | 10 | mW/°C | DIP8, above TA = 25°C | 4 | |||
| Power rating, DIP8 package | 680 | mW | DIP8, TA = 70°C | 4 | |||
| Threshold voltage | VIT | 0.95 | 1.33 | 1.65 | V | VDD = 2 V, TA = 25°C | 5 |
| Threshold voltage | VIT | 0.85 | 1.75 | V | VDD = 2 V, full range 0°C to 70°C | 5 | |
| Trigger voltage | VI(TRIG) | 0.4 | 0.67 | 0.95 | V | VDD = 2 V, TA = 25°C | 5 |
| Trigger voltage | VI(TRIG) | 0.3 | 1.05 | V | VDD = 2 V, full range 0°C to 70°C | 5 | |
| Reset voltage | VI(RESET) | 0.4 | 1.1 | 1.5 | V | VDD = 2 V, TA = 25°C | 5 |
| Reset voltage | VI(RESET) | 0.3 | 1.8 | V | VDD = 2 V, full range 0°C to 70°C | 5 | |
| Threshold voltage | VIT | 2.8 | 3.3 | 3.8 | V | VDD = 5 V, TA = 25°C | 6 |
| Threshold voltage | VIT | 2.7 | 3.9 | V | VDD = 5 V, full range 0°C to 70°C | 6 | |
| Trigger voltage | VI(TRIG) | 1.36 | 1.66 | 1.96 | V | VDD = 5 V, TA = 25°C | 6 |
| Trigger voltage | VI(TRIG) | 1.26 | 2.06 | V | VDD = 5 V, full range 0°C to 70°C | 6 | |
| Reset voltage | VI(RESET) | 0.4 | 1.1 | 1.5 | V | VDD = 5 V, TA = 25°C | 6 |
| Reset voltage | VI(RESET) | 0.3 | 1.8 | V | VDD = 5 V, full range 0°C to 70°C | 6 | |
| Threshold voltage | VIT | 9.45 | 10.55 | V | VDD = 15 V, TA = 25°C | 7 | |
| Threshold voltage | VIT | 9.35 | 10.65 | V | VDD = 15 V, full range 0°C to 70°C | 7 | |
| Trigger voltage | VI(TRIG) | 4.65 | 5 | 5.35 | V | VDD = 15 V, TA = 25°C | 7 |
| Trigger voltage | VI(TRIG) | 4.55 | 5.45 | V | VDD = 15 V, full range 0°C to 70°C | 7 | |
| Reset voltage | VI(RESET) | 0.4 | 1.1 | 1.5 | V | VDD = 15 V, TA = 25°C | 7 |
| Reset voltage | VI(RESET) | 0.3 | 1.8 | V | VDD = 15 V, full range 0°C to 70°C | 7 |
CAD (KiCad official)
- Symbol:
XD551 - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
xd551-etched.step/xd551-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd551.step/xd551.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (12 pp, sha256
8c2a047422caeea7, retrieved 2026-10-14, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).