# XD4538

**XINLUDA** · Monostable Multivibrators · DIP-16

XD4538 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | T1A | passive | External timing component pin of monostable A (RX/CX network); the datasheet gives no further detail for this pin. |
| 2 | T2A | passive | Timing node of monostable A where external RX and CX connect; the voltage here is described as pin 2 in the retrigger operation, with input capacitance 10 pF. |
| 3 | CDA | input | Active-LOW latched reset input of monostable A; while held low it inhibits triggers and forces Q low. |
| 4 | AA INPUT | input | Trigger input A of monostable A, a valid trigger is recognized on a VSS-to-VDD rising edge while B and CD are at VDD. |
| 5 | BA INPUT | input | Trigger input B of monostable A, a valid trigger is recognized on a VDD-to-VSS falling edge while A is at VSS and CD is at VDD. |
| 6 | QA OUT | output | Q output of monostable A, normally low and high for the timed pulse; symmetrical sink and source capability. |
| 7 | Q̄A OUT | output | Complementary (inverted) Q output of monostable A, with symmetrical sink and source capability. |
| 8 | VSS | power_in | Ground supply pin (VSS = 0 V). |
| 9 | Q̄B OUT | output | Complementary (inverted) Q output of monostable B, with symmetrical sink and source capability. |
| 10 | QB OUT | output | Q output of monostable B, normally low and high for the timed pulse; symmetrical sink and source capability. |
| 11 | BB INPUT | input | Trigger input B of monostable B, a valid trigger is recognized on a VDD-to-VSS falling edge while A is at VSS and CD is at VDD. |
| 12 | AB INPUT | input | Trigger input A of monostable B, a valid trigger is recognized on a VSS-to-VDD rising edge while B and CD are at VDD. |
| 13 | CDB | input | Active-LOW latched reset input of monostable B; while held low it inhibits triggers and forces Q low. |
| 14 | T2B | passive | Timing node of monostable B where external RX and CX connect; the voltage here is described as pin 14 in the retrigger operation, with input capacitance 10 pF. |
| 15 | T1B | passive | External timing component pin of monostable B (RX/CX network); the datasheet gives no further detail for this pin. |
| 16 | VDD | power_in | Positive supply pin, recommended 3 to 15 VDC, absolute maximum 18 VDC. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage (absolute maximum) | VDD | -0.5 |  | 18 | V |  | 6 |
| Input Voltage (absolute maximum, referenced to VDD) | VIN | -0.5 |  |  | V | Printed as VDD + 0.5 V; no numeric max | 6 |
| Storage Temperature Range | TS | -65 |  | 150 | °C |  | 6 |
| Power Dissipation, Dual-In-Line | PD |  |  | 700 | mW | Dual-In-Line package | 6 |
| Lead Temperature | TL |  |  | 260 | °C | Soldering, 10 seconds | 6 |
| DC Supply Voltage (recommended) | VDD | 3 |  | 15 | V |  | 6 |
| Input Voltage (recommended) | VIN | 0 |  |  | V | Printed as 0 to VDD; max is VDD, not a number | 6 |
| Operating Temperature Range | TA | -40 |  | 85 | °C |  | 6 |
| External Timing Resistance | RX | 5 |  |  | kΩ | Max: No limit (Note 5) | 7 |
| External Timing Capacitance | CX | 0 |  |  | pF | Max: No limit (Note 5) | 7 |
| Quiescent Device Current | IDD |  |  | 20 | µA | VDD=5V, VIH=VDD, VIL=VSS, all outputs open; max at -40°C | 6 |
| Quiescent Device Current | IDD |  |  | 40 | µA | VDD=10V, VIH=VDD, VIL=VSS, all outputs open; max at -40°C | 6 |
| Quiescent Device Current | IDD |  |  | 80 | µA | VDD=15V, VIH=VDD, VIL=VSS, all outputs open; max at -40°C | 6 |
| Quiescent Device Current | IDD |  |  | 150 | µA | VDD=5V, VIH=VDD, VIL=VSS, all outputs open; max at 85°C | 6 |
| Quiescent Device Current | IDD |  |  | 300 | µA | VDD=10V, VIH=VDD, VIL=VSS, all outputs open; max at 85°C | 6 |
| Quiescent Device Current | IDD |  |  | 600 | µA | VDD=15V, VIH=VDD, VIL=VSS, all outputs open; max at 85°C | 6 |
| LOW Level Output Voltage | VOL |  | 0 | 0.05 | V | VDD=5V, /IO/=1µA; max at 25°C | 6 |
| HIGH Level Output Voltage | VOH | 4.95 | 5 |  | V | VDD=5V, /IO/=1µA; min at 25°C | 6 |
| HIGH Level Output Voltage | VOH | 9.95 | 10 |  | V | VDD=10V, /IO/=1µA, VIH=VDD, VIL=VSS; min at 25°C | 6 |
| HIGH Level Output Voltage | VOH | 14.95 | 15 |  | V | VDD=15V, /IO/=1µA, VIH=VDD, VIL=VSS; min at 25°C | 6 |
| LOW Level Input Voltage | VIL |  | 2.25 | 1.5 | V | VDD=5V, /IO/=1µA, VO=0.5V or 4.5V; max at 25°C | 6 |
| LOW Level Input Voltage | VIL |  | 4.5 | 3 | V | VDD=10V, /IO/=1µA, VO=1.0V or 9.0V; max at 25°C | 6 |
| LOW Level Input Voltage | VIL |  | 6.75 | 4 | V | VDD=15V, /IO/=1µA, VO=1.5V or 13.5V; max at 25°C | 6 |
| HIGH Level Input Voltage | VIH | 3.5 | 2.75 |  | V | VDD=5V, /IO/=1µA, VO=0.5V or 4.5V; min at 25°C | 6 |
| HIGH Level Input Voltage | VIH | 7 | 5.5 |  | V | VDD=10V, /IO/=1µA, VO=1.0V or 9.0V; min at 25°C | 6 |
| HIGH Level Input Voltage | VIH | 11 | 8.25 |  | V | VDD=15V, /IO/=1µA, VO=1.5V or 13.5V; min at 25°C | 6 |
| LOW Level Output Current (Note 3) | IOL | 0.44 | 0.88 |  | mA | VDD=5V, VO=0.4V, VIH=VDD; min at 25°C | 6 |
| LOW Level Output Current (Note 3) | IOL | 1.1 | 2.25 |  | mA | VDD=10V, VO=0.5V, VIL=VSS; min at 25°C | 6 |
| LOW Level Output Current (Note 3) | IOL | 3 | 8.8 |  | mA | VDD=15V, VO=1.5V; min at 25°C | 6 |
| HIGH Level Output Current (Note 3) | IOH | 0.44 | 0.88 |  | mA | VDD=5V, VO=4.6V, VIL=VSS; min at 25°C | 6 |
| HIGH Level Output Current (Note 3) | IOH | 1.1 | 2.25 |  | mA | VDD=10V, VO=9.5V, VIL=VSS; min at 25°C | 6 |
| HIGH Level Output Current (Note 3) | IOH | 3 | 8.8 |  | mA | VDD=15V, VO=13.5V; min at 25°C | 6 |
| Output Transition Time | tTLH, tTHL |  | 100 | 200 | ns | VDD=5V; TA=25°C, CL=50pF, tr=tf=20ns | 7 |
| Output Transition Time | tTLH, tTHL |  | 50 | 100 | ns | VDD=10V; TA=25°C, CL=50pF, tr=tf=20ns | 7 |
| Output Transition Time | tTLH, tTHL |  | 40 | 80 | ns | VDD=15V; TA=25°C, CL=50pF, tr=tf=20ns | 7 |
| Propagation Delay Time, Trigger (A or B to Q or Q-bar) | tPLH, tPHL |  | 300 | 600 | ns | VDD=5V; TA=25°C, CL=50pF | 7 |
| Propagation Delay Time, Trigger (A or B to Q or Q-bar) | tPLH, tPHL |  | 150 | 300 | ns | VDD=10V; TA=25°C, CL=50pF | 7 |
| Propagation Delay Time, Trigger (A or B to Q or Q-bar) | tPLH, tPHL |  | 100 | 220 | ns | VDD=15V; TA=25°C, CL=50pF | 7 |
| Propagation Delay Time, Reset (CD to Q or Q-bar) | tPLH, tPHL |  | 250 | 500 | ns | VDD=5V; TA=25°C, CL=50pF | 7 |
| Propagation Delay Time, Reset (CD to Q or Q-bar) | tPLH, tPHL |  | 125 | 250 | ns | VDD=10V; TA=25°C, CL=50pF | 7 |
| Propagation Delay Time, Reset (CD to Q or Q-bar) | tPLH, tPHL |  | 95 | 190 | ns | VDD=15V; TA=25°C, CL=50pF | 7 |
| Minimum Input Pulse Width (A, B, or CD) | tWL, tWH |  | 35 | 70 | ns | VDD=5V; TA=25°C | 7 |
| Minimum Input Pulse Width (A, B, or CD) | tWL, tWH |  | 30 | 60 | ns | VDD=10V; TA=25°C | 7 |
| Minimum Input Pulse Width (A, B, or CD) | tWL, tWH |  | 25 | 50 | ns | VDD=15V; TA=25°C | 7 |
| Input Capacitance, Other Inputs | CIN |  | 5 | 7.5 | pF | Other inputs | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 208 | 226 | 244 | s | RX=100k, CX=0.002µF, VDD=5V (see Figure 6) | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 211 | 230 | 248 | s | RX=100k, CX=0.002µF, VDD=10V (see Figure 6) | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 216 | 235 | 254 | s | RX=100k, CX=0.002µF, VDD=15V (see Figure 6) | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 8.83 | 9.6 | 10.37 | ms | RX=100k, CX=0.1µF, VDD=5V | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 9.02 | 9.8 | 10.59 | ms | RX=100k, CX=0.1µF, VDD=10V | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 9.2 | 10 | 10.8 | ms | RX=100k, CX=0.1µF, VDD=15V | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 0.87 | 0.95 | 1.03 | s | RX=100k, CX=10.0µF, VDD=5V | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 0.89 | 0.97 | 1.05 | s | RX=100k, CX=10.0µF, VDD=10V | 7 |
| Output Pulse Width (Q or Q-bar) | PWOUT | 0.91 | 0.99 | 1.07 | s | RX=100k, CX=10.0µF, VDD=15V | 7 |
| Pulse Width Match between Circuits in the Same Package |  |  |  | 1 | % | RX=100k, CX=0.1µF, VDD=5V | 7 |
| Input Capacitance, Pin 2 or 14 | CIN |  | 10 |  | pF | Pin 2 or 14 | 7 |

## CAD (KiCad official)

- Symbol: `XD4538`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `xd4538-etched.step` / `xd4538-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xd4538.step` / `xd4538.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588905868905885696) (11 pp, sha256 `c87e093569e5ce95`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xd4538-datasheet.pdf)