component
XD4518
Public Made by Adomby adom
XINLUDA Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD4518
XINLUDA · Counters, Dividers · DIP-16
XD4518 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLOCK A | input | Clock input of counter A, advancing on the positive-going edge when ENABLE A is high. |
| 2 | ENABLE A | input | Enable input of counter A, which increments on a negative-going transition when CLOCK A is low and is held high for single-unit operation. |
| 3 | Q1A | output | Counter A BCD output stage 1. |
| 4 | Q2A | output | Counter A BCD output stage 2. |
| 5 | Q3A | output | Counter A BCD output stage 3. |
| 6 | Q4A | output | Counter A BCD output stage 4, which can be connected to the next enable input for ripple-mode cascading. |
| 7 | RESET A | input | Reset input of counter A, where a high level clears Q1 through Q4 to 0. |
| 8 | VSS | power_in | Ground/negative supply terminal, which is the reference for the voltage ratings. |
| 9 | CLOCK B | input | Clock input of counter B, advancing on the positive-going edge when ENABLE B is high. |
| 10 | ENABLE B | input | Enable input of counter B, which increments on a negative-going transition when CLOCK B is low and is held high for single-unit operation. |
| 11 | Q1B | output | Counter B BCD output stage 1. |
| 12 | Q2B | output | Counter B BCD output stage 2. |
| 13 | Q3B | output | Counter B BCD output stage 3. |
| 14 | Q4B | output | Counter B BCD output stage 4, which can be connected to the next enable input for ripple-mode cascading. |
| 15 | RESET B | input | Reset input of counter B, where a high level clears Q1 through Q4 to 0. |
| 16 | VDD | power_in | Positive supply voltage, with a recommended range of 3 V to 18 V and an absolute maximum of -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
XD4518 - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
xd4518-etched.step/xd4518-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd4518.step/xd4518.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (6 pp, sha256
1232a405f0933cb5, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).