component
XD4069
Public Made by Adomby adom
XINLUDA Inverters, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
XD4069
XINLUDA · Inverters · DIP-14
XD4069 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input of inverter 1; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 2 | 1Y | output | Output of inverter 1; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 3 | 2A | input | Input of inverter 2; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 4 | 2Y | output | Output of inverter 2; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 5 | 3A | input | Input of inverter 3; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 6 | 3Y | output | Output of inverter 3; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 7 | VSS | power_in | Ground reference (0 V); all supply and input voltages are referenced to this pin. |
| 8 | 4Y | output | Output of inverter 4; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 9 | 4A | input | Input of inverter 4; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 10 | 5Y | output | Output of inverter 5; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 11 | 5A | input | Input of inverter 5; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 12 | 6Y | output | Output of inverter 6; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 13 | 6A | input | Input of inverter 6; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 14 | VDD | power_in | Supply voltage, recommended 3 V to 15 V referenced to VSS; absolute maximum supply voltage is 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage | VDD | -0.5 | 18 | V | 4 | ||
| IIK input clamping current | IIK | 10 | mA | VI < 0.5 V or VI > VDD + 0.5 V | 4 | ||
| VI input voltage | VI | -0.5 | V | 4 | |||
| IOK output clamping current | IOK | 10 | mA | VO < 0.5 V or VO > VDD + 0.5 V | 4 | ||
| input/output current | II/O | 10 | mA | 4 | |||
| supply current | IDD | 50 | mA | 4 | |||
| storage temperature | Tstg | -50 | 150 | C | 4 | ||
| ambient temperature | Tamb | -25 | 85 | C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = 25 C to +85 C; DIP14 (XD4069) | 4 | ||
| power dissipation per output | P | 100 | mW | 4 | |||
| supply voltage | VDD | 3 | 15 | V | 4 | ||
| input voltage | VI | 0 | V | 4 | |||
| ambient temperature in free air | Tamb | -25 | 85 | C | 4 | ||
| HIGH-level input voltage | VIH | 4 | V | IO < 1 µA; VDD = 5 V; Tamb = +25 C | 5 | ||
| HIGH-level input voltage | VIH | 8 | V | IO < 1 µA; VDD = 10 V; Tamb = +25 C | 5 | ||
| HIGH-level input voltage | VIH | 12.5 | V | IO < 1 µA; VDD = 15 V; Tamb = +25 C | 5 | ||
| LOW-level input voltage | VIL | 1 | V | IO < 1 µA; VDD = 5 V; Tamb = +25 C | 5 | ||
| LOW-level input voltage | VIL | 2 | V | IO < 1 µA; VDD = 10 V; Tamb = +25 C | 5 | ||
| LOW-level input voltage | VIL | 2.5 | V | IO < 1 µA; VDD = 15 V; Tamb = +25 C | 5 | ||
| HIGH-level output voltage | VOH | 4.95 | V | IO < 1 µA; VDD = 5 V; Tamb = +25 C | 5 | ||
| HIGH-level output voltage | VOH | 9.95 | V | IO < 1 µA; VDD = 10 V; Tamb = +25 C | 5 | ||
| HIGH-level output voltage | VOH | 14.95 | V | IO < 1 µA; VDD = 15 V; Tamb = +25 C | 5 | ||
| LOW-level output voltage | VOL | 0.05 | V | IO < 1 µA; VDD = 5 V; Tamb = +25 C | 5 | ||
| HIGH-level output current | IOH | -1.4 | mA | VO = 2.5 V; VDD = 5 V; Tamb = +25 C | 5 | ||
| HIGH-level output current | IOH | -0.5 | mA | VO = 4.6 V; VDD = 5 V; Tamb = +25 C | 5 | ||
| HIGH-level output current | IOH | -1.3 | mA | VO = 9.5 V; VDD = 10 V; Tamb = +25 C | 5 | ||
| HIGH-level output current | IOH | -3.4 | mA | VO = 13.5 V; VDD = 15 V; Tamb = +25 C | 5 | ||
| LOW-level output current | IOL | 0.5 | mA | VO = 0.4 V; VDD = 5 V; Tamb = +25 C | 5 | ||
| LOW-level output current | IOL | 1.3 | mA | VO = 0.5 V; VDD = 10 V; Tamb = +25 C | 5 | ||
| LOW-level output current | IOL | 3.4 | mA | VO = 1.5 V; VDD = 15 V; Tamb = +25 C | 5 | ||
| input leakage current | II | 0.1 | µA | VDD = 15 V; Tamb = +25 C | 5 | ||
| supply current | IDD | 0.4 | µA | all valid input combinations; IO = 0 A; VDD = 5 V; Tamb = +25 C | 5 | ||
| supply current | IDD | 1.2 | µA | all valid input combinations; IO = 0 A; VDD = 10 V; Tamb = +25 C | 5 | ||
| supply current | IDD | 2.5 | µA | all valid input combinations; IO = 0 A; VDD = 15 V; Tamb = +25 C | 5 | ||
| input capacitance | CI | 7.5 | pF | digital inputs; Tamb = +25 C | 5 | ||
| HIGH to LOW propagation delay nA to nY | tPHL | 45 | 90 | ns | Tamb = 25 C; VDD = 5 V | 6 | |
| HIGH to LOW propagation delay nA to nY | tPHL | 20 | 40 | ns | Tamb = 25 C; VDD = 10 V | 6 | |
| HIGH to LOW propagation delay nA to nY | tPHL | 15 | 25 | ns | Tamb = 25 C; VDD = 15 V | 6 | |
| LOW to HIGH propagation delay nA to nY | tPLH | 40 | 80 | ns | Tamb = 25 C; VDD = 5 V | 6 | |
| LOW to HIGH propagation delay nA to nY | tPLH | 20 | 40 | ns | Tamb = 25 C; VDD = 10 V | 6 | |
| LOW to HIGH propagation delay nA to nY | tPLH | 15 | 30 | ns | Tamb = 25 C; VDD = 15 V | 6 | |
| HIGH to LOW output transition time nY | tTHL | 60 | 120 | ns | Tamb = 25 C; VDD = 5 V | 6 | |
| HIGH to LOW output transition time nY | tTHL | 30 | 60 | ns | Tamb = 25 C; VDD = 10 V | 6 | |
| HIGH to LOW output transition time nY | tTHL | 20 | 40 | ns | Tamb = 25 C; VDD = 15 V | 6 | |
| LOW to HIGH output transition time nY | tTLH | 60 | 120 | ns | Tamb = 25 C; VDD = 5 V | 6 | |
| LOW to HIGH output transition time nY | tTLH | 30 | 60 | ns | Tamb = 25 C; VDD = 10 V | 6 | |
| LOW to HIGH output transition time nY | tTLH | 20 | 40 | ns | Tamb = 25 C; VDD = 15 V | 6 |
CAD (KiCad official)
- Symbol:
XD4069 - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
xd4069-etched.step/xd4069-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd4069.step/xd4069.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (12 pp, sha256
aee9efd5f0380b82, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# XD4069
**XINLUDA** · Inverters · DIP-14
XD4069 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input of inverter 1; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 2 | 1Y | output | Output of inverter 1; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 3 | 2A | input | Input of inverter 2; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 4 | 2Y | output | Output of inverter 2; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 5 | 3A | input | Input of inverter 3; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 6 | 3Y | output | Output of inverter 3; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 7 | VSS | power_in | Ground reference (0 V); all supply and input voltages are referenced to this pin. |
| 8 | 4Y | output | Output of inverter 4; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 9 | 4A | input | Input of inverter 4; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 10 | 5Y | output | Output of inverter 5; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 11 | 5A | input | Input of inverter 5; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 12 | 6Y | output | Output of inverter 6; absolute maximum input/output current is 10 mA and power dissipation per output is 100 mW. |
| 13 | 6A | input | Input of inverter 6; input voltage must stay between 0 V and VDD, and unused inputs must be connected to VDD, VSS, or another input. |
| 14 | VDD | power_in | Supply voltage, recommended 3 V to 15 V referenced to VSS; absolute maximum supply voltage is 18 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage | VDD | -0.5 | | 18 | V | | 4 |
| IIK input clamping current | IIK | | | 10 | mA | VI < 0.5 V or VI > VDD + 0.5 V | 4 |
| VI input voltage | VI | -0.5 | | | V | | 4 |
| IOK output clamping current | IOK | | | 10 | mA | VO < 0.5 V or VO > VDD + 0.5 V | 4 |
| input/output current | II/O | | | 10 | mA | | 4 |
| supply current | IDD | | | 50 | mA | | 4 |
| storage temperature | Tstg | -50 | | 150 | C | | 4 |
| ambient temperature | Tamb | -25 | | 85 | C | | 4 |
| total power dissipation | Ptot | | | 500 | mW | Tamb = 25 C to +85 C; DIP14 (XD4069) | 4 |
| power dissipation per output | P | | | 100 | mW | | 4 |
| supply voltage | VDD | 3 | | 15 | V | | 4 |
| input voltage | VI | 0 | | | V | | 4 |
| ambient temperature in free air | Tamb | -25 | | 85 | C | | 4 |
| HIGH-level input voltage | VIH | 4 | | | V | IO < 1 µA; VDD = 5 V; Tamb = +25 C | 5 |
| HIGH-level input voltage | VIH | 8 | | | V | IO < 1 µA; VDD = 10 V; Tamb = +25 C | 5 |
| HIGH-level input voltage | VIH | 12.5 | | | V | IO < 1 µA; VDD = 15 V; Tamb = +25 C | 5 |
| LOW-level input voltage | VIL | | | 1 | V | IO < 1 µA; VDD = 5 V; Tamb = +25 C | 5 |
| LOW-level input voltage | VIL | | | 2 | V | IO < 1 µA; VDD = 10 V; Tamb = +25 C | 5 |
| LOW-level input voltage | VIL | | | 2.5 | V | IO < 1 µA; VDD = 15 V; Tamb = +25 C | 5 |
| HIGH-level output voltage | VOH | 4.95 | | | V | IO < 1 µA; VDD = 5 V; Tamb = +25 C | 5 |
| HIGH-level output voltage | VOH | 9.95 | | | V | IO < 1 µA; VDD = 10 V; Tamb = +25 C | 5 |
| HIGH-level output voltage | VOH | 14.95 | | | V | IO < 1 µA; VDD = 15 V; Tamb = +25 C | 5 |
| LOW-level output voltage | VOL | | | 0.05 | V | IO < 1 µA; VDD = 5 V; Tamb = +25 C | 5 |
| HIGH-level output current | IOH | -1.4 | | | mA | VO = 2.5 V; VDD = 5 V; Tamb = +25 C | 5 |
| HIGH-level output current | IOH | -0.5 | | | mA | VO = 4.6 V; VDD = 5 V; Tamb = +25 C | 5 |
| HIGH-level output current | IOH | -1.3 | | | mA | VO = 9.5 V; VDD = 10 V; Tamb = +25 C | 5 |
| HIGH-level output current | IOH | -3.4 | | | mA | VO = 13.5 V; VDD = 15 V; Tamb = +25 C | 5 |
| LOW-level output current | IOL | 0.5 | | | mA | VO = 0.4 V; VDD = 5 V; Tamb = +25 C | 5 |
| LOW-level output current | IOL | 1.3 | | | mA | VO = 0.5 V; VDD = 10 V; Tamb = +25 C | 5 |
| LOW-level output current | IOL | 3.4 | | | mA | VO = 1.5 V; VDD = 15 V; Tamb = +25 C | 5 |
| input leakage current | II | | | 0.1 | µA | VDD = 15 V; Tamb = +25 C | 5 |
| supply current | IDD | | | 0.4 | µA | all valid input combinations; IO = 0 A; VDD = 5 V; Tamb = +25 C | 5 |
| supply current | IDD | | | 1.2 | µA | all valid input combinations; IO = 0 A; VDD = 10 V; Tamb = +25 C | 5 |
| supply current | IDD | | | 2.5 | µA | all valid input combinations; IO = 0 A; VDD = 15 V; Tamb = +25 C | 5 |
| input capacitance | CI | | | 7.5 | pF | digital inputs; Tamb = +25 C | 5 |
| HIGH to LOW propagation delay nA to nY | tPHL | | 45 | 90 | ns | Tamb = 25 C; VDD = 5 V | 6 |
| HIGH to LOW propagation delay nA to nY | tPHL | | 20 | 40 | ns | Tamb = 25 C; VDD = 10 V | 6 |
| HIGH to LOW propagation delay nA to nY | tPHL | | 15 | 25 | ns | Tamb = 25 C; VDD = 15 V | 6 |
| LOW to HIGH propagation delay nA to nY | tPLH | | 40 | 80 | ns | Tamb = 25 C; VDD = 5 V | 6 |
| LOW to HIGH propagation delay nA to nY | tPLH | | 20 | 40 | ns | Tamb = 25 C; VDD = 10 V | 6 |
| LOW to HIGH propagation delay nA to nY | tPLH | | 15 | 30 | ns | Tamb = 25 C; VDD = 15 V | 6 |
| HIGH to LOW output transition time nY | tTHL | | 60 | 120 | ns | Tamb = 25 C; VDD = 5 V | 6 |
| HIGH to LOW output transition time nY | tTHL | | 30 | 60 | ns | Tamb = 25 C; VDD = 10 V | 6 |
| HIGH to LOW output transition time nY | tTHL | | 20 | 40 | ns | Tamb = 25 C; VDD = 15 V | 6 |
| LOW to HIGH output transition time nY | tTLH | | 60 | 120 | ns | Tamb = 25 C; VDD = 5 V | 6 |
| LOW to HIGH output transition time nY | tTLH | | 30 | 60 | ns | Tamb = 25 C; VDD = 10 V | 6 |
| LOW to HIGH output transition time nY | tTLH | | 20 | 40 | ns | Tamb = 25 C; VDD = 15 V | 6 |
## CAD (KiCad official)
- Symbol: `XD4069`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files: `xd4069-etched.step` / `xd4069-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xd4069.step` / `xd4069.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588896652832198656) (12 pp, sha256 `aee9efd5f0380b82`, retrieved 2026-10-15, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/xd4069-datasheet.pdf)