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XD4060

Public Made by Adom

by adom

XINLUDA Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD4060

XINLUDA · Counters, Dividers · DIP-16

XD4060 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q12 output Buffered counter output of stage 12.
2 Q13 output Buffered counter output of stage 13.
3 Q14 output Buffered counter output of stage 14, the last stage of the 14-stage ripple counter.
4 Q6 output Buffered counter output of stage 6.
5 Q5 output Buffered counter output of stage 5.
6 Q7 output Buffered counter output of stage 7.
7 Q4 output Buffered counter output of stage 4.
8 VSS power_in Ground supply pin, VSS = 0V.
9 φ0 output Oscillator pin connecting to the timing capacitor Cx in the RC oscillator; not covered by the output current ratings.
10 φ0 (inverted) output Inverted oscillator output pin connecting to resistor R1 in the RC oscillator; not covered by the output current ratings.
11 φ1 input Clock input with Schmitt trigger; counter advances on the negative clock transition, and R2 connects here in the RC oscillator.
12 RESET input Master reset input; a logical 1 resets the counter to zero independent of clock.
13 Q9 output Buffered counter output of stage 9.
14 Q8 output Buffered counter output of stage 8.
15 Q10 output Buffered counter output of stage 10.
16 VDD power_in Positive supply pin, recommended 3V to 15V, absolute maximum 18V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (absolute maximum) VDD -0.5 18 V VSS = 0V (Note 1) 3
Input Voltage (absolute maximum) VIN -0.5 V Upper limit printed as VDD + 0.5V 3
Storage Temperature Range TS -65 150 °C 3
Package Dissipation PD 700 mW N Package 3
Package Dissipation PD 500 mW M Package 3
Lead Temperature (soldering) TL 260 °C Soldering, 10 seconds 3
Supply Voltage (recommended) VDD 3 15 V 3
Input Voltage (recommended) VIN 0 V Upper limit printed as VDD 3
Operating Temperature Range TA -40 85 °C 3
Quiescent Device Current IDD 5 µA TA = +25°C; VDD = 5V, VIN = VDD or VSS 4
Quiescent Device Current IDD 10 µA TA = +25°C; VDD = 10V, VIN = VDD or VSS 4
Quiescent Device Current IDD 20 µA TA = +25°C; VDD = 15V, VIN = VDD or VSS 4
LOW Level Output Voltage VOL 0 0.05 V TA = +25°C; VDD = 5V 4
HIGH Level Output Voltage VOH 4.95 5 V TA = +25°C; VDD = 5V 4
HIGH Level Output Voltage VOH 9.95 10 V TA = +25°C; VDD = 10V 4
HIGH Level Output Voltage VOH 14.95 15 V TA = +25°C; VDD = 15V 4
LOW Level Input Voltage VIL 1.5 V TA = +25°C; VDD = 5V, VO = 0.5V or 4.5V 4
LOW Level Input Voltage VIL 3 V TA = +25°C; VDD = 10V, VO = 1.0V or 9.0V 4
LOW Level Input Voltage VIL 4 V TA = +25°C; VDD = 15V, VO = 1.5V or 13.5V 4
HIGH Level Input Voltage VIH 3.5 V TA = +25°C; VDD = 5V, VO = 0.5V or 4.5V 4
HIGH Level Input Voltage VIH 7 V TA = +25°C; VDD = 10V, VO = 1.0V or 9.0V 4
HIGH Level Input Voltage VIH 11 V TA = +25°C; VDD = 15V, VO = 1.5V or 13.5V 4
LOW Level Output Current IOL 0.51 0.88 mA TA = +25°C; VDD = 5V, VO = 0.4V 4
LOW Level Output Current IOL 1.3 2.25 mA TA = +25°C; VDD = 10V, VO = 0.5V 4
LOW Level Output Current IOL 3.4 8.8 mA TA = +25°C; VDD = 15V, VO = 1.5V 4
HIGH Level Output Current IOH -0.51 -0.88 mA TA = +25°C; VDD = 5V, VO = 4.6V 4
HIGH Level Output Current IOH -1.3 -2.25 mA TA = +25°C; VDD = 10V, VO = 9.5V 4
HIGH Level Output Current IOH -3.4 -8.8 mA TA = +25°C; VDD = 15V, VO = 13.5V 4
Input Current IIN -10 -5 -0.1 µA TA = +25°C; VDD = 15V, VIN = 0V 4
Input Current IIN 10 -5 0.1 µA TA = +25°C; VDD = 15V, VIN = 15V 4
Propagation Delay Time to Q4 (tPHL4, tPLH4) tPHL4, tPLH4 550 1300 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 5V 5
Propagation Delay Time to Q4 (tPHL4, tPLH4) tPHL4, tPLH4 250 525 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 10V 5
Propagation Delay Time to Q4 (tPHL4, tPLH4) tPHL4, tPLH4 200 400 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 15V 5
Interstage Propagation Delay Time from Qn to Qn+1 (tPHL, tPLH) tPHL, tPLH 150 330 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 5V 5
Interstage Propagation Delay Time from Qn to Qn+1 (tPHL, tPLH) tPHL, tPLH 60 125 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 10V 5
Interstage Propagation Delay Time from Qn to Qn+1 (tPHL, tPLH) tPHL, tPLH 45 90 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 15V 5
Transition Time (tTHL, tTLH) tTHL, tTLH 100 200 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 5V 5
Transition Time (tTHL, tTLH) tTHL, tTLH 50 100 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 10V 5
Transition Time (tTHL, tTLH) tTHL, tTLH 40 80 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 15V 5
Minimum Clock Pulse Width (tWL, tWH) tWL, tWH 170 500 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 5V 5
Minimum Clock Pulse Width (tWL, tWH) tWL, tWH 65 170 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 10V 5
Minimum Clock Pulse Width (tWL, tWH) tWL, tWH 50 125 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 15V 5
Maximum Clock Frequency (fCL) fCL 1 3 MHZ TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 5V 5
Maximum Clock Frequency (fCL) fCL 3 8 MHZ TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 10V 5
Maximum Clock Frequency (fCL) fCL 4 10 MHZ TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 15V 5
Reset Propagation Delay tPHL(R) 200 450 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 5V 5
Reset Propagation Delay tPHL(R) 100 210 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 10V 5
Reset Propagation Delay tPHL(R) 80 170 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 15V 5
Minimum Reset Pulse Width (tWH(R)) tWH(R) 200 450 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 5V 5
Minimum Reset Pulse Width (tWH(R)) tWH(R) 100 210 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 10V 5
Minimum Reset Pulse Width (tWH(R)) tWH(R) 80 170 ns TA = 25°C, CL = 50pF, RL = 200k, tr = tf = 20 ns; VDD = 15V 5
Average Input Capacitance CIN 5 7.5 pF Any Input 5
Power Dissipation Capacitance CPD 50 pF 5

CAD (KiCad official)

  • Symbol: XD4060
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd4060-etched.step / xd4060-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd4060.step / xd4060.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (6 pp, sha256 fee59d4e8b5091d7, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF