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XD4052

Public Made by Adom

by adom

XINLUDA Signal Switches, Multiplexers, Decoders, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD4052

XINLUDA · Signal Switches, Multiplexers, Decoders · DIP-16

XD4052 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 0Y bidirectional Channel 0 analog input/output of the Y switch group, connected to common Y (pin 3) when A=0, B=0 and INH=0.
2 2Y bidirectional Channel 2 analog input/output of the Y switch group, connected to common Y when B=1, A=0 and INH=0.
3 Y bidirectional Common Y analog output/input of the Y four-channel switch.
4 3Y bidirectional Channel 3 analog input/output of the Y switch group, connected to common Y when B=1, A=1 and INH=0.
5 1Y bidirectional Channel 1 analog input/output of the Y switch group, connected to common Y when B=0, A=1 and INH=0.
6 INH input Inhibit input; logic 1 turns all channels of both switch groups off, logic 0 allows the channel selected by A and B to be on, with a 4.5V to 18V digital level.
7 VEE power_in Negative analog supply; analog signals may swing down to VEE, with VDD-VEE up to 18V.
8 VSS power_in Digital ground reference, 0V in the datasheet examples.
9 B input Binary address select input B, with a 4.5V to 18V digital level, selecting one of four channels in both groups.
10 A input Binary address select input A, with a 4.5V to 18V digital level, selecting one of four channels in both groups.
11 3X bidirectional Channel 3 analog input/output of the X switch group, connected to common X (pin 13) when B=1, A=1 and INH=0.
12 0X bidirectional Channel 0 analog input/output of the X switch group, connected to common X when A=0, B=0 and INH=0.
13 X bidirectional Common X analog output/input of the X four-channel switch.
14 1X bidirectional Channel 1 analog input/output of the X switch group, connected to common X when B=0, A=1 and INH=0.
15 2X bidirectional Channel 2 analog input/output of the X switch group, connected to common X when B=1, A=0 and INH=0.
16 VDD power_in Positive supply; recommended 5V to 15V, absolute maximum -0.5 to +18V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC supply voltage VDD -0.5 18 V 3
Input voltage VIN -0.5 V 3
Operating temperature range Ta -40 85 ℃ 3
Power dissipation (DIP) Ptot 700 mW DIP package 3
Welding temperature TL 260 ℃ 3
DC supply voltage VDD 5 15 V 3
Input voltage VIN 0 V 3
Static current IDD 5 uA T=25℃, VDD=5V 4
Static current IDD 10 uA T=25℃, VDD=10V 4
Static current IDD 20 uA T=25℃, VDD=15V 4
On-resistance RON 270 1050 Ω T=25℃, RL=10KΩ (either channel), VDD=2.5V, VEE=-2.5V or VDD=5V, VEE=0V 4
On-resistance RON 120 400 Ω T=25℃, RL=10KΩ (either channel), VDD=5V, VEE=-5V or VDD=10V, VEE=0V 4
On-resistance RON 80 240 Ω T=25℃, RL=10KΩ (either channel), VDD=7.5V, VEE=-7.5V or VDD=15V, VEE=0V 4
Transmission delay time from disable to signal output (open channel) tPZH, tPZL 600 1200 ns VEE=VSS=0V, RL=1KΩ, CL=50pF, VDD=5V 5
Transmission delay time from disable to signal output (open channel) tPZH, tPZL 225 450 ns VEE=VSS=0V, RL=1KΩ, CL=50pF, VDD=10V 5
Transmission delay time from disable to signal output (open channel) tPZH, tPZL 160 320 ns VEE=VSS=0V, RL=1KΩ, CL=50pF, VDD=15V 5
Transmission delay time from disable to signal output (closed channel) tPHZ, tPLZ 210 420 ns VEE=VSS=0V, RL=1KΩ, CL=50pF, VDD=5V 5
Transmission delay time from disable to signal output (closed channel) tPHZ, tPLZ 100 200 ns VEE=VSS=0V, RL=1KΩ, CL=50pF, VDD=10V 5
Transmission delay time from disable to signal output (closed channel) tPHZ, tPLZ 75 150 ns VEE=VSS=0V, RL=1KΩ, CL=50pF, VDD=15V 5
Input capacitance (control input) Cin 5 7.5 pF VDD=10V 5
Input capacitance (signal input) Cin 10 15 pF VDD=10V 5
Transmission delay time from input to output tPHL, tPLH 25 55 ns VEE=VSS=0V, CL=50pF, VDD=5V 6
Transmission delay time from input to output tPHL, tPLH 15 35 ns VEE=VSS=0V, CL=50pF, VDD=10V 6
Transmission delay time from input to output tPHL, tPLH 10 25 ns VEE=VSS=0V, CL=50pF, VDD=15V 6
Transmission delay time from the access to the signal output channel is on or off tPHL, tPLH 500 1000 ns VEE=VSS=0V, CL=50pF, VDD=5V 6
Transmission delay time from the access to the signal output channel is on or off tPHL, tPLH 160 350 ns VEE=VSS=0V, CL=50pF, VDD=10V 6
Transmission delay time from the access to the signal output channel is on or off tPHL, tPLH 120 240 ns VEE=VSS=0V, CL=50pF, VDD=15V 6

CAD (KiCad official)

  • Symbol: XD4052
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd4052-etched.step / xd4052-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd4052.step / xd4052.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (9 pp, sha256 90929b303d449f0f, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF