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XD4051

Public Made by Adom

by adom

XINLUDA Signal Switches, Multiplexers, Decoders, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD4051

XINLUDA · Signal Switches, Multiplexers, Decoders · DIP-16

XD4051 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 4 bidirectional Analog channel 4 input/output, switched to the common pin when ABC = 100 (C=1, B=0, A=0) and INH = 0.
2 6 bidirectional Analog channel 6 input/output, switched to the common pin when ABC = 110 and INH = 0.
3 OUT/IN bidirectional Common analog output/input pin shared by the eight channels.
4 7 bidirectional Analog channel 7 input/output, switched to the common pin when ABC = 111 and INH = 0.
5 5 bidirectional Analog channel 5 input/output, switched to the common pin when ABC = 101 and INH = 0.
6 INH input Inhibit input: logic 1 turns all channels off, logic 0 allows the channel selected by A, B and C to be on; input voltage range is -0.5 V to VDD+0.5 V.
7 VEE power_in Negative analog supply that sets the lower limit of the switched analog signal, for example VEE = -13.5 V in the datasheet example.
8 VSS power_in Ground/digital reference supply pin (VSS = 0 V in the datasheet examples).
9 C input Binary address input C (most significant bit) selecting one of the 8 channels, with a 4.5 V to 18 V logic level.
10 B input Binary address input B selecting one of the 8 channels, with a 4.5 V to 18 V logic level.
11 A input Binary address input A (least significant bit) selecting one of the 8 channels, with a 4.5 V to 18 V logic level.
12 3 bidirectional Analog channel 3 input/output, switched to the common pin when ABC = 011 and INH = 0.
13 0 bidirectional Analog channel 0 input/output, switched to the common pin when ABC = 000 and INH = 0.
14 1 bidirectional Analog channel 1 input/output, switched to the common pin when ABC = 001 and INH = 0.
15 2 bidirectional Analog channel 2 input/output, switched to the common pin when ABC = 010 and INH = 0.
16 VDD power_in Positive supply voltage, recommended +5 V to +15 V and absolute maximum -0.5 V to +18 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC supply voltage VDD -0.5 18 V 3
Input voltage VIN -0.5 V 3
Operating temperature range Ta -40 85 ℃ 3
Power dissipation Ptot 700 mW DIP package 3
Welding temperature TL 260 ℃ 3
DC supply voltage VDD 5 15 V 3
Input voltage VIN 0 V 3
Static current IDD 5 uA VDD=5V 4
Static current IDD 10 uA VDD=10V 4
Static current IDD 20 uA VDD=15V 4
On-resistance RON 270 1050 Ω RL=10KΩ (either channel), peak VEE≦VIS≦VDD; VDD=2.5V, VEE=-2.5V or VDD=5V, VEE=0V 4
On-resistance RON 120 400 Ω RL=10KΩ (either channel), peak VEE≦VIS≦VDD; VDD=5V, VEE=-5V or VDD=10V, VEE=0V 4
On-resistance RON 80 240 Ω RL=10KΩ (either channel), peak VEE≦VIS≦VDD; VDD=7.5V, VEE=-7.5V or VDD=15V, VEE=0V 4
Transmission delay time from disable to signal output (open channel) tPZH, tPZL 600 1200 ns VDD=5V, VEE=VSS=0V, RL=1KΩ, CL=50pF 5
Transmission delay time from disable to signal output (open channel) tPZH, tPZL 225 450 ns VDD=10V, VEE=VSS=0V, RL=1KΩ, CL=50pF 5
Transmission delay time from disable to signal output (open channel) tPZH, tPZL 160 320 ns VDD=15V, VEE=VSS=0V, RL=1KΩ, CL=50pF 5
Transmission delay time from disable to signal output (closed channel) tPHZ, tPLZ 210 420 ns VDD=5V, VEE=VSS=0V, RL=1KΩ, CL=50pF 5
Transmission delay time from disable to signal output (closed channel) tPHZ, tPLZ 100 200 ns VDD=10V, VEE=VSS=0V, RL=1KΩ, CL=50pF 5
Transmission delay time from disable to signal output (closed channel) tPHZ, tPLZ 75 150 ns VDD=15V, VEE=VSS=0V, RL=1KΩ, CL=50pF 5
Input capacitance (control input) Cin 5 7.5 pF 5
Input capacitance (signal input) Cin 10 15 pF 5
The transmission delay of a signal from input to output tPHL, tPLH 25 55 ns VDD=5V, VEE=VSS=0V, CL=50pF 6
The transmission delay of a signal from input to output tPHL, tPLH 15 35 ns VDD=10V, VEE=VSS=0V, CL=50pF 6
The transmission delay of a signal from input to output tPHL, tPLH 10 25 ns VDD=15V, VEE=VSS=0V, CL=50pF 6
The transmission delay time from the access to the signal output channel is on or off tPHL, tPLH 500 1000 ns VDD=5V, VEE=VSS=0V, CL=50pF 6
The transmission delay time from the access to the signal output channel is on or off tPHL, tPLH 160 350 ns VDD=10V, VEE=VSS=0V, CL=50pF 6
The transmission delay time from the access to the signal output channel is on or off tPHL, tPLH 120 240 ns VDD=15V, VEE=VSS=0V, CL=50pF 6

CAD (KiCad official)

  • Symbol: XD4051
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd4051-etched.step / xd4051-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd4051.step / xd4051.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (9 pp, sha256 dbba2c2c77bbf4dd, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF