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XD40192

Public Made by Adom

by adom

XINLUDA Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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XD40192

XINLUDA · Counters, Dividers · DIP-16

XD40192 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 J2 input Jam (preset) data input for bit 2, loaded asynchronously into Q2 when PRESET ENABLE is low.
2 Q2 output Buffered counter output for bit 2.
3 Q1 output Buffered counter output for bit 1.
4 CLOCK DOWN input Count-down clock input; counter decrements on the positive edge provided CLOCK UP is high.
5 CLOCK UP input Count-up clock input; counter increments on the positive edge provided CLOCK DOWN is high.
6 Q3 output Buffered counter output for bit 3.
7 Q4 output Buffered counter output for bit 4.
8 VSS power_in Ground (GND) supply pin, 0V reference.
9 J4 input Jam (preset) data input for bit 4, loaded asynchronously into Q4 when PRESET ENABLE is low.
10 J3 input Jam (preset) data input for bit 3, loaded asynchronously into Q3 when PRESET ENABLE is low.
11 PRESET ENABLE input Active-low asynchronous preset control that loads each output with the level on its jam input when low.
12 CARRY output Active-low carry output that goes low one-half clock cycle after maximum count in count-up mode, for cascading to the next CLOCK UP.
13 BORROW output Active-low borrow output that goes low one-half clock cycle after minimum count in count-down mode, for cascading to the next CLOCK DOWN.
14 RESET input Master asynchronous reset; a high level clears all outputs low.
15 J1 input Jam (preset) data input for bit 1, loaded asynchronously into Q1 when PRESET ENABLE is low.
16 VDD power_in Positive supply voltage; absolute maximum -0.5V to +20V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Current IDD 10 µA Ta = 25°C; VDD = 20V, VIN = VDD or GND 3
Input Leakage Current IIL -100 nA Ta = 25°C; VIN = VDD or GND, VDD = 20V 3
Input Leakage Current IIH 100 nA Ta = 25°C; VIN = VDD or GND, VDD = 20V 3
Output Voltage (low) VOL 50 mV Ta = 25°C; VDD = 15V, No Load 3
Output Voltage (high) VOH 14.95 V Ta = 25°C; VDD = 15V, No Load (Note 3) 3
Output Current (Sink) 5V IOL 0.53 mA Ta = 25°C; VDD = 5V, VOUT = 0.4V 3
Output Current (Sink) 10V IOL 1.4 mA Ta = 25°C; VDD = 10V, VOUT = 0.5V 3
Output Current (Sink) 15V IOL 3.5 mA Ta = 25°C; VDD = 15V, VOUT = 1.5V 3
Output Current (Source) 5A IOH -0.53 mA Ta = 25°C; VDD = 5V, VOUT = 4.6V 3
Output Current (Source) 5B IOH -1.8 mA Ta = 25°C; VDD = 5V, VOUT = 2.5V 3
Output Current (Source) 10V IOH -1.4 mA Ta = 25°C; VDD = 10V, VOUT = 9.5V 3
Output Current (Source) 15V IOH -3.5 mA Ta = 25°C; VDD = 15V, VOUT = 13.5V 3
N Threshold Voltage VNTH -2.8 -0.7 V Ta = 25°C; VDD = 10V, ISS = -10µA 3
P Threshold Voltage VPTH 0.7 2.8 V Ta = 25°C; VSS = 0V, IDD = 10µA 3
Input Voltage Low (5V) VIL 1.5 V Ta = 25°C; VDD = 5V, VOH > 4.5V, VOL < 0.5V 3
Input Voltage High (5V) VIH 3.5 V Ta = 25°C; VDD = 5V, VOH > 4.5V, VOL < 0.5V 3
Input Voltage Low (15V) VIL 4 V Ta = 25°C; VDD = 15V, VOH > 13.5V, VOL < 1.5V 3
Input Voltage High (15V) VIH 11 V Ta = 25°C; VDD = 15V, VOH > 13.5V, VOL < 1.5V 3
Propagation Delay Clock Up or Clock Down to Q TPHL1/TPLH1 500 ns Ta = 25°C; VDD = 5V, VIN = VDD or GND (CL = 50pF, RL = 200K, Input TR, TF < 20ns) 4
Propagation Delay Reset to Q TPHL2 500 ns Ta = 25°C; VDD = 5V, VIN = VDD or GND 4
Propagation Delay PE to Q TPHL3/TPLH3 400 ns Ta = 25°C; VDD = 5V, VIN = VDD or GND 4
Propagation Delay Clock Up to Carry, Clock Down to Borrow TPHL4/TPLH4 320 ns Ta = 25°C; VDD = 5V, VIN = VDD or GND 4
Propagation Delay PE to Borrow or Carry TPHL5/TPLH5 600 ns Ta = 25°C; VDD = 5V, VIN = VDD or GND 4
Propagation Delay Reset to Borrow or Carry TPHL6/TPLH6 600 ns Ta = 25°C; VDD = 5V, VIN = VDD or GND 4
Transition Time TPHL/TPLH 200 ns Ta = 25°C; VDD = 5V, VIN = VDD or GND 4
Maximum Clock Input Frequency FCL 2 MHZ Ta = 25°C; VDD = 5V, VIN = VDD or GND 4
Supply Current 5V IDD 5 µA VDD = 5V, VIN = VDD or GND, +25°C 5
Supply Current 10V IDD 10 µA VDD = 10V, VIN = VDD or GND, +25°C 5
Supply Current 15V IDD 10 µA VDD = 15V, VIN = VDD or GND, +25°C 5
Output Voltage (low) 5V VOL 50 mV VDD = 5V, No Load, +25°C 5
Output Voltage (low) 10V VOL 50 mV VDD = 10V, No Load, +25°C 5
Output Voltage (high) 5V VOH 4.95 V VDD = 5V, No Load, +25°C 5
Output Voltage (high) 10V VOH 9.95 V VDD = 10V, No Load, +25°C 5
Input Voltage Low VIL 3 V VDD = 10V, VOH > 9V, VOL < 1V, +25°C 5
Input Voltage High VIH 7 V VDD = 10V, VOH > 9V, VOL < 1V, +25°C 5
Propagation Delay Clock Up or Down to Q 10V TPHL1/TPLH1 240 ns VDD = 10V, +25°C 5
Propagation Delay Clock Up or Down to Q 15V TPHL1/TPLH1 180 ns VDD = 15V, +25°C 5
Propagation Delay Reset to Q 10V TPHL2 240 ns VDD = 10V, +25°C 5
Propagation Delay Reset to Q 15V TPHL2 180 ns VDD = 15V, +25°C 5
Propagation Delay PE to Q 10V TPHL3/TPLH3 200 ns VDD = 10V, +25°C 5
Propagation Delay PE to Q 15V TPHL3/TPLH3 140 ns VDD = 15V, +25°C 5
Transition Time 10V TPHL1/TPLH1 100 ns VDD = 10V, +25°C 5
Transition Time 15V TPHL1/TPLH1 80 ns VDD = 15V, +25°C 5
Maximum Clock Rise and Fall Time 5V TPCL 15 µs VDD = 5V, +25°C 5
Maximum Clock Rise and Fall Time 10V TPCL 15 µs VDD = 10V, +25°C 5
Maximum Clock Rise and Fall Time 15V TPCL 5 µs VDD = 15V, +25°C 5
Minimum Removal Time Reset or PE 5V TREM 80 ns VDD = 5V, +25°C 5
Minimum Removal Time Reset or PE 10V TREM 40 ns VDD = 10V, +25°C 5
Minimum Removal Time Reset or PE 15V TREM 30 ns VDD = 15V, +25°C 5
Minimum Clock Pulse Width 5V TW 180 ns VDD = 5V, +25°C 5
Minimum Clock Pulse Width 10V TW 90 ns VDD = 10V, +25°C 5
Minimum Clock Pulse Width 15V TW 60 ns VDD = 15V, +25°C 5
Input Capacitance Reset CIN 15 pF +25°C 5
Input Capacitance All Other Inputs CIN 7.5 pF +25°C 5
DC Supply Voltage Range VDD -0.5 20 V 3
Input Voltage Range, All Inputs VIN -0.5 V Upper limit printed as VDD + 0.5V 3
DC Input Current, Any One Input IIN -10 10 mA Printed as ±10mA 3
Operating Temperature Range TA -40 85 °C 3
Storage Temperature Range TSTG -65 150 °C 3
Lead Temperature (During Soldering) 265 °C 3

CAD (KiCad official)

  • Symbol: XD40192
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd40192-etched.step / xd40192-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd40192.step / xd40192.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (13 pp, sha256 4e9f950857f7d976, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF