component
XD3526
Public Made by Adomby adom
XINLUDA AC-DC Controllers & Regulators, DIP-18. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD3526
XINLUDA · AC-DC Controllers & Regulators · DIP-18
XD3526 from XINLUDA, in a DIP-18. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | +Error | input | Non-inverting input of the error amplifier, specified for a common-mode voltage range of 0 V to +5.2 V. |
| 2 | -Error | input | Inverting input of the error amplifier, specified for a common-mode voltage range of 0 V to +5.2 V. |
| 3 | Compensation | input | Error amplifier output/compensation node that sets PWM duty cycle, with minimum duty cycle 0% at +0.4 V and maximum duty cycle 45% min / 49% typ at +3.6 V. |
| 4 | CSoft-Start | passive | Soft-start capacitor connection, charged at 50 µA min, 100 µA typ, 150 µA max when Reset is +2.4 V. |
| 5 | Reset | bidirectional | Digital reset port, TTL and B-series CMOS compatible, with output low level up to 0.4 V at 3.6 mA sink and high level at least 2.4 V. |
| 6 | -CS | input | Inverting input of the current limit comparator, specified for a common-mode range of 0 V to +12 V. |
| 7 | +CS | input | Non-inverting input of the current limit comparator, specified for a common-mode range of 0 V to +12 V with a sense voltage of 80 mV min, 100 mV typ, 120 mV max. |
| 8 | Shutdown | bidirectional | Digital shutdown port, TTL and B-series CMOS compatible; input low-level current is up to -360 µA at VIL = +0.4 V. |
| 9 | RT | passive | Oscillator timing resistor connection, with RT specified from 2.0 kΩ to 150 kΩ. |
| 10 | CT | passive | Oscillator timing capacitor connection, with CT specified from 0.001 µF to 20 µF. |
| 11 | RDeadtime | passive | Dead-time programming connection, with available dead-time range of 3.0% min to 50% max at 40 kHz. |
| 12 | Sync | bidirectional | Digital sync port for synchronizing the oscillator, TTL and B-series CMOS compatible, with output high level at least 2.4 V and low level up to 0.4 V. |
| 13 | Output A | output | Totem-pole output driver A, rated for ±100 mA sink/source per output (±200 mA absolute maximum). |
| 14 | VC | power_in | Collector supply for the output drivers, specified from 4.5 V to 35 V. |
| 15 | Ground | power_in | Ground return for the device. |
| 16 | Output B | output | Totem-pole output driver B, rated for ±100 mA sink/source per output (±200 mA absolute maximum). |
| 17 | VCC | power_in | Supply voltage input, specified from 8.0 V to 35 V for operation (+40 V absolute maximum). |
| 18 | Vref | power_out | Trimmed 5.0 V ±1% reference output, rated for up to 20 mA load current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-18 |
| Category | Power Management ICs |
| Pins | 18 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 40 | Vdc | 2 | |||
| Collector Supply Voltage | VC | 40 | Vdc | 2 | |||
| Logic Inputs | -0.3 | 5.5 | V | 2 | |||
| Analog Inputs | -0.3 | V | 2 | ||||
| Output Current, Source or Sink (each output) | IO | -200 | 200 | mA | 2 | ||
| Reference Load Current | Iref | 50 | mA | VCC = 40 V | 2 | ||
| Logic Sink Current | 15 | mA | 2 | ||||
| Power Dissipation | PD | 1000 | mW | TA = +25°C | 2 | ||
| Power Dissipation | PD | 3000 | mW | TC = +25°C | 2 | ||
| Operating Junction Temperature | TJ | 150 | °C | 2 | |||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 2 | ||
| Supply Voltage | VCC | 8 | 35 | Vdc | 2 | ||
| Collector Supply Voltage | VC | 4.5 | 35 | Vdc | 2 | ||
| Output Sink/Source Current (each output) | IO | 0 | 100 | mA | 2 | ||
| Reference Load Current | Iref | 0 | 20 | mA | 2 | ||
| Oscillator Frequency Range | fosc | 0.001 | 400 | kHz | 2 | ||
| Oscillator Timing Resistor | RT | 2 | 150 | kΩ | 2 | ||
| Oscillator Timing Capacitor | CT | 0.001 | 20 | μF | 2 | ||
| Available Deadtime Range | 3 | 50 | % | 40 kHz | 2 | ||
| Operating Junction Temperature Range | TJ | 0 | 125 | °C | 2 | ||
| Reference Output Voltage | Vref | 4.9 | 5 | 5.1 | V | TJ = +25°C | 3 |
| Line Regulation | Regline | 10 | 30 | mV | +8.0 V ≤ VCC ≤ +35 V | 3 | |
| Load Regulation | Regload | 10 | 50 | mV | 0 mA ≤ IL ≤ 20 mA | 3 | |
| Total Reference Output Voltage Variation | ΔVref | 4.85 | 5 | 5.15 | V | +8.0 V ≤ VCC ≤ +35 V, 0 mA ≤ IL ≤ 20 mA | 3 |
| Short Circuit Current | ISC | 25 | 80 | 125 | mA | Vref = 0 V | 3 |
| Reset Output Voltage | 0.2 | 0.4 | V | Vref = +3.8 V | 3 | ||
| Reset Output Voltage | 2.4 | 4.8 | V | Vref = +4.8 V | 3 | ||
| Initial Accuracy | -8 | 3 | 8 | % | TJ = +25°C | 3 | |
| Frequency Stability over Power Supply Range | Δfosc/ΔVCC | 0.5 | 1 | % | +8.0 V ≤ VCC ≤ +35 V | 3 | |
| Maximum Frequency | fmax | 400 | kHz | RT = 2.0 kΩ, CT = 0.001 μF | 3 | ||
| Sawtooth Peak Voltage | Vosc(P) | 3 | 3.5 | V | VCC = +35 V | 3 | |
| Sawtooth Valley Voltage | Vosc(V) | 0.45 | 0.8 | V | VCC = +8.0 V | 3 | |
| Input Offset Voltage | VIO | 2 | 10 | mV | RS ≤ 2.0 kΩ | 3 | |
| Input Bias Current | IIB | -350 | -2000 | nA | 3 | ||
| Input Offset Current | IIO | 35 | 200 | nA | 3 | ||
| DC Open Loop Gain | AVOL | 60 | 72 | dB | RL ≥ 10 MΩ | 3 | |
| High Output Voltage (error amplifier) | VOH | 3.6 | 4.2 | V | VPin 1−VPin 2 ≥ +150 mV, Isource = 100 μA | 3 | |
| Low Output Voltage (error amplifier) | VOL | 0.2 | 0.4 | V | VPin 2−VPin 1 ≥ +150 mV, Isink = 100 μA | 3 | |
| Common Mode Rejection Ratio | CMRR | 70 | 94 | dB | RS ≤ 2.0 kΩ | 3 | |
| Power Supply Rejection Ratio | PSRR | 66 | 80 | dB | +12 V ≤ VCC ≤ +18 V | 3 | |
| Minimum Duty Cycle | DCmin | 0 | % | VCompensation = +0.4 V | 4 | ||
| Maximum Duty Cycle | DCmax | 45 | 49 | % | VCompensation = +3.6 V | 4 | |
| Digital Port Output Voltage High Logic Level (SYNC, SHUTDOWN, RESET) | VOH | 2.4 | 4 | V | Isource = 40 μA | 4 | |
| Digital Port Output Voltage Low Logic Level (SYNC, SHUTDOWN, RESET) | VOL | 0.2 | 0.4 | V | Isink = 3.6 mA | 4 | |
| Input Current High Logic Level (SYNC, SHUTDOWN, RESET) | IIH | -125 | -200 | μA | VIH = +2.4 V | 4 | |
| Input Current Low Logic Level (SYNC, SHUTDOWN, RESET) | IIL | -225 | -360 | μA | VIL = +0.4 V | 4 | |
| Sense Voltage | Vsense | 80 | 100 | 120 | mV | RS ≤ 50 Ω | 4 |
| Current Limit Input Bias Current | IIB | -3 | -10 | μA | 4 | ||
| Error Clamp Voltage | 0.1 | 0.4 | V | Reset = +0.4 V | 4 | ||
| CSoft-Start Charging Current | ICS | 50 | 100 | 150 | μA | Reset = +2.4 V | 4 |
| Output High Level | VOH | 12.5 | 13.5 | V | Isource = 20 mA | 4 | |
| Output High Level | VOH | 12 | 13 | V | Isource = 100 mA | 4 | |
| Output Low Level | VOL | 0.2 | 0.3 | V | Isink = 20 mA | 4 | |
| Output Low Level | VOL | 1.2 | 2 | V | Isink = 100 mA | 4 | |
| Collector Leakage | IC(leak) | 50 | 150 | μA | VC = +40 V | 4 | |
| Rise Time | tr | 0.3 | 0.6 | μs | CL = 1000 pF | 4 | |
| Fall Time | tf | 0.1 | 0.2 | μs | CL = 1000 pF | 4 | |
| Supply Current | ICC | 18 | 30 | mA | Shutdown = +0.4 V, VCC = +35 V, RT = 4.12 kΩ | 4 | |
| Thermal Resistance Junction-to-Air | RθJA | 100 | °C/W | 2 | |||
| Thermal Resistance Junction-to-Case | RθJC | 42 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
XD3526 - Footprint:
Package_DIP:DIP-18_W7.62mm - 3D model: DIP-18 (KiCad packages3D, STEP)
- 3D model files:
xd3526-etched.step/xd3526-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd3526.step/xd3526.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (10 pp, sha256
0ed5a9697e83d371, retrieved 2026-10-29, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).