component
XD3525
Public Made by Adomby adom
XINLUDA AC-DC Controllers & Regulators, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD3525
XINLUDA · AC-DC Controllers & Regulators · DIP-16
XD3525 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INV. INPUT | input | Inverting input of the error amplifier, whose input common-mode range includes the 5.1 V reference. |
| 2 | N.I. INPUT | input | Non-inverting input of the error amplifier, whose input common-mode range includes the 5.1 V reference. |
| 3 | SYNC | input | Oscillator sync input that lets multiple units be slaved or one unit be synchronized to an external clock, with a 1.2 to 2.8 V threshold. |
| 4 | OSC. OUTPUT | output | Oscillator output providing the clock signal, with a clock amplitude of 3 to 3.5 V. |
| 5 | CT | passive | Oscillator timing capacitor terminal, recommended 0.001 µF to 0.1 µF. |
| 6 | RT | passive | Oscillator timing resistor terminal, recommended 2 K to 150 K. |
| 7 | DISCHARGE | passive | Oscillator discharge terminal; a single resistor between CT and this pin sets dead time, with a recommended range of 0 to 500 Ω. |
| 8 | SOFT-START | passive | Soft-start terminal with a current-source pullup, where an external capacitor sets the soft-start time and a pull-down of at most 100 µA turns off the outputs. |
| 9 | COMP | bidirectional | Error amplifier output (compensation) terminal with a current-source pullup, where a pull-down of at most 100 µA turns off the outputs. |
| 10 | SHUTDOWN | input | Shutdown input where a positive signal immediately sets the PWM latch and starts a 150 µA soft-start capacitor discharge; it should not be left floating. |
| 11 | OUTPUT A | output | Totem-pole output A that can source or sink in excess of 200 mA. |
| 12 | GROUND | power_in | Ground reference. |
| 13 | VC | power_in | Collector supply voltage for the output stages, recommended 4.5 to 35 V. |
| 14 | OUTPUT B | output | Totem-pole output B that can source or sink in excess of 200 mA. |
| 15 | +Vi | power_in | Supply voltage input, recommended 8 to 35 V. |
| 16 | VREF | power_out | +5.1 V reference output trimmed to ±1 %, with a reference load current of 0 to 20 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Power Management ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | Vi | 40 | V | 4 | |||
| Collector Supply Voltage | VC | 40 | V | 4 | |||
| Oscillator Charging Current | IOSC | 5 | mA | 4 | |||
| Output Current, Source or Sink | Io | 500 | mA | 4 | |||
| Reference Output Current | IR | 50 | mA | 4 | |||
| Current through CT Terminal | IT | 5 | mA | 4 | |||
| Logic Inputs | -0.3 | 5.5 | V | 4 | |||
| Analog Inputs | -0.3 | 35 | V | upper limit printed as Vi | 4 | ||
| Total Power Dissipation | Ptot | 1000 | mW | Tamb = 70 °C | 4 | ||
| Junction Temperature Range | Tj | -55 | 150 | °C | 4 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 4 | ||
| Operating Ambient Temperature | Top | -40 | 85 | °C | XL3525K | 4 | |
| Input Voltage | Vi | 8 | 35 | V | 4 | ||
| Collector Supply Voltage | VC | 4.5 | 35 | V | 4 | ||
| Sink/Source Load Current (steady state) | 0 | 100 | mA | 4 | |||
| Sink/Source Load Current (peak) | 0 | 400 | mA | 4 | |||
| Reference Load Current | 0 | 20 | mA | 4 | |||
| Oscillator Timing Resistor | RT | 2 | 150 | kΩ | 2 K to 150 K | 4 | |
| Oscillator Timing Capacitor | CT | 0.001 | 0.1 | µF | 4 | ||
| Reference Output Voltage | VREF | 5 | 5.1 | 5.2 | V | Tj = 25 °C | 5 |
| VREF Line Regulation | 10 | 20 | mV | Vi = 8 to 35 V | 5 | ||
| VREF Load Regulation | 20 | 50 | mV | IL = 0 to 20 mA | 5 | ||
| VREF Temp. Stability | ΔVREF/ΔT | 20 | 50 | mV | Over Operating Range | 5 | |
| Total Output Variation | 4.95 | 5.25 | V | Line, Load and Temperature | 5 | ||
| Short Circuit Current | 80 | 100 | mA | VREF = 0, Tj = 25 °C | 5 | ||
| Oscillator Initial Accuracy | -6 | 2 | 6 | % | Tj = 25 °C; typ printed ±2, limits ±6 | 5 | |
| Oscillator Voltage Stability | -2 | 1 | 2 | % | Vi = 8 to 35 V; typ printed ±1, limits ±2 | 5 | |
| Oscillator Temperature Stability | Δf/ΔT | -6 | 3 | 6 | % | Over Operating Range; typ printed ±3, limits ±6 | 5 |
| Minimum Frequency | fMIN | 120 | Hz | RT = 200 K, CT = 0.1 µF | 5 | ||
| Maximum Frequency | fMAX | 400 | kHz | RT = 2 K, CT = 470 pF | 5 | ||
| Current Mirror | 1.7 | 2 | 2.2 | mA | IRT = 2 mA | 5 | |
| Clock Width | 0.3 | 0.5 | 1 | µs | Tj = 25 °C | 5 | |
| Sync Threshold | 1.2 | 2 | 2.8 | V | 5 | ||
| Sync Input Current | 1 | 2.5 | mA | Sync Voltage = 3.5 V | 5 | ||
| Input Offset Voltage | VOS | 2 | 10 | mV | VCM = 5.1 V | 5 | |
| Input Bias Current | Ib | 1 | 10 | µA | VCM = 5.1 V | 5 | |
| DC Open Loop Gain | 60 | 75 | dB | RL ≥ 10 MΩ | 5 | ||
| Error Amp Output Low Level | 0.2 | 0.5 | V | VCM = 5.1 V | 5 | ||
| Error Amp Output High Level | 3.8 | 5.6 | V | VCM = 5.1 V | 5 | ||
| Common Mode Rejection | CMR | 60 | 75 | dB | VCM = 1.5 to 5.2 V | 5 | |
| Supply Voltage Rejection | PSR | 50 | 60 | dB | Vi = 8 to 35 V | 5 | |
| Minimum Duty-cycle | 0 | % | 6 | ||||
| Maximum Duty-cycle | 45 | 49 | % | 6 | |||
| Input Threshold, Zero Duty-cycle | 0.7 | 0.9 | V | 6 | |||
| Input Threshold, Maximum Duty-cycle | 3.3 | 3.6 | V | 6 | |||
| Soft Start Current | 25 | 50 | 80 | µA | VSD = 0 V, VSS = 0 V | 6 | |
| Soft Start Low Level | 0.4 | 0.7 | V | VSD = 2.5 V | 6 | ||
| Shutdown Threshold | 0.6 | 0.8 | 1 | V | To outputs, VSS = 5.1 V, Tj = 25 °C | 6 | |
| Shutdown Input Current | 0.4 | 1 | mA | VSD = 2.5 V | 6 | ||
| Output Low Level | 0.2 | 0.4 | V | Isink = 20 mA | 6 | ||
| Output Low Level | 1 | 2 | V | Isink = 100 mA | 6 | ||
| Output High Level | 18 | 19 | V | Isource = 20 mA | 6 | ||
| Output High Level | 17 | 18 | V | Isource = 100 mA | 6 | ||
| Under-Voltage Lockout | 6 | 7 | 8 | V | Vcomp and Vss = High | 6 | |
| Collector Leakage | IC | 200 | µA | VC = 35 V | 6 | ||
| Rise Time | tr | 100 | 600 | ns | CL = 1 nF, Tj = 25 °C | 6 | |
| Fall Time | tf | 50 | 300 | ns | CL = 1 nF, Tj = 25 °C | 6 | |
| Supply Current | Is | 14 | 20 | mA | Vi = 35 V | 6 |
CAD (KiCad official)
- Symbol:
XD3525 - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
xd3525-etched.step/xd3525-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd3525.step/xd3525.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (14 pp, sha256
1a99ad128cc09d00, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).