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XD3485
Public Made by Adomby adom
XINLUDA RS-485 / RS-422 ICs, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD3485
XINLUDA · RS-485 / RS-422 ICs · DIP-8
XD3485 from XINLUDA, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RO | output | Receiver output: when /RE is low, RO is high if A-B is at or above +200 mV and low if A-B is at or below -200 mV. |
| 2 | RE | input | Receiver output enable, active low: RO is active when /RE is low and high-impedance when /RE is high; with /RE high and DE low the device enters low-power shutdown. |
| 3 | DE | input | Driver output enable, active high: the driver output is active when DE is high and highly resistive when DE is low; with /RE high and DE low the device enters low-power shutdown. |
| 4 | DI | input | Driver input: when DE is high, a low on DI drives output A low and B high, and a high on DI drives A high and B low. |
| 5 | GND | power_in | Ground; the reference point for all voltages on the device. |
| 6 | A | bidirectional | Receiver non-inverting input and driver non-inverting output on the bus; bus-side input voltage is limited to -7 V to 13 V. |
| 7 | B | bidirectional | Receiver inverting input and driver inverting output on the bus; bus-side input voltage is limited to -7 V to 13 V. |
| 8 | VCC | power_in | Power supply, 3.3 V nominal with a stated operating range of 3.0 V to 3.6 V; absolute maximum supply voltage is +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-8 |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 7 | V | 3 | |||
| Control Port Voltage (RE, DE, DI) | -0.3 | 7 | V | 3 | |||
| Bus-side input voltage (A, B) | -7 | 13 | V | 3 | |||
| Receiver output voltage (RO) | -0.3 | 7 | V | 3 | |||
| Operating Temperature Range | -40 | 85 | ℃ | 3 | |||
| Storage operating temperature range | -55 | 150 | ℃ | 3 | |||
| Welding temperature range | 300 | ℃ | 3 | ||||
| Continuous power consumption | 700 | mW | DIP-8 package | 3 | |||
| Operating voltage range | VCC | 3 | 3.6 | V | 1 | ||
| Input current (A, B) | IIN2 | 125 | uA | DE = 0 V, VCC=0 or 3.3V, VIN = 12 V | 4 | ||
| Input current (A, B) | IIN2 | -100 | uA | DE = 0 V, VCC=0 or 3.3V, VIN = -7 V | 4 | ||
| Drive Differential Outputs | VOD2 | 1.5 | V | Figure 2, RL = 54 Ω; printed max is the symbol VCC | 4 | ||
| Drive Differential Outputs | VOD2 | 2 | V | Figure 2, RL = 100 Ω; printed max is the symbol VCC | 4 | ||
| Change in output voltage amplitude | ΔVOD | 0.2 | V | Figure 2, RL = 54 Ω | 4 | ||
| Output common mode voltage | VOC | 3 | V | Figure 2, RL = 54 Ω | 4 | ||
| Change in common mode output voltage amplitude | ΔVOC | 0.2 | V | Figure 2, RL = 54 Ω | 4 | ||
| High Level Input | VIH | 2 | V | DE, DI, RE | 4 | ||
| Low Level Input | VIL | 0.8 | V | DE, DI, RE | 4 | ||
| Logic Input Current | IIN1 | -2 | 2 | uA | DE, DI, RE | 4 | |
| Current at output short-circuit, short-circuit to high | IOSD1 | 250 | mA | Short circuit to 0V~12V | 4 | ||
| Current at output short-circuit, short-circuit to low | IOSD2 | -250 | mA | Short circuit to -7V~0V | 4 | ||
| Supply Current | ICC1 | 520 | 800 | uA | RE=0V, DE = 0 V | 5 | |
| Supply Current | ICC2 | 540 | 700 | uA | RE=VCC, DE=VCC | 5 | |
| Shutdown current | ISHDN | 0.5 | 10 | uA | RE=VCC, DE=0V | 5 | |
| Driver differential output delay | tDD | 10 | 35 | ns | RDIFF = 60 Ω, CL1=CL2=100pF (See Figure 3 and 4) | 5 | |
| Driver Differential Output Transition Time | tTD | 12 | 25 | ns | 5 | ||
| Drive propagation delay from low to high | tPLH | 8 | 35 | ns | RDIFF = 27 Ω, (See Figure 3 and 4) | 5 | |
| Drive propagation delay from high to low | tPHL | 8 | 35 | ns | 5 | ||
| Forward Input Threshold Voltage | VIT+ | 200 | mV | -7V≦VCM≦12V | 5 | ||
| Reverse Input Threshold Voltage | VIT- | -200 | mV | -7V≦VCM≦12V | 5 | ||
| Input Hysteresis Voltage | Vhys | 10 | 30 | mV | -7V≦VCM≦12V | 5 | |
| Low Level Output Voltage | VOL | 0.4 | V | IOUT = +2.5mA, VID = -200 mV | 5 | ||
| Tri-state input leakage current | IOZR | -1 | 1 | uA | 0.4 V < VO < 2.4 V | 5 | |
| Receiver input resistance | RIN | 96 | kΩ | -7V≦VCM≦12V | 5 | ||
| Receiver short-circuit current | IOSR | 8 | 60 | mA | 0 V≤VO≤VCC | 5 | |
| Receiver /tPLH-tPHL/ skew | tPDS | 1 | 8 | ns | 6 | ||
| Enable to Output High | tPZH | 20 | 90 | ns | RL= 110Ω, (See Figure 5、6) | 6 | |
| Enable to Output Low | tPZL | 20 | 90 | ns | RL= 110Ω, (See Figure 5、6) | 6 | |
| Input low to forbidden energy | tPLZ | 20 | 80 | ns | RL= 110Ω, (See Figure 5、6) | 6 | |
| Input high to forbidden energy | tPHZ | 20 | 80 | ns | RL= 110Ω, (See Figure 5、6) | 6 | |
| Off condition, Enable to output high | tDSH | 500 | 900 | ns | RL= 110Ω, (See Figure 5、6) | 6 | |
| Off condition, Enable to output low | tDSL | 500 | 900 | ns | RL= 110Ω, (See Figure 5、6) | 6 | |
| Receiver input to output propagation delay from low to high | tRPLH | 80 | 150 | ns | CL=15pF, See Figure 7 and Figure 8 | 6 | |
| Receiver input to output propagation delay from high to low | tRPHL | 80 | 150 | ns | CL=15pF, See Figure 7 and Figure 8 | 6 | |
| Receiver /tRPLH − tRPHL/ skew | tRPDS | 7 | 10 | ns | 6 | ||
| Enable to Output Low Time | tRPZL | 20 | 50 | ns | CL=15pF, See Figure 7 and Figure 8 | 6 | |
| Enable to Output High Time | tRPZH | 20 | 50 | ns | CL=15pF, See Figure 7 and Figure 8 | 6 | |
| From low output to disabled time | tPRLZ | 20 | 45 | ns | CL=15pF, See Figure 7 and Figure 8 | 6 | |
| From high output to disablement time | tPRHZ | 20 | 45 | ns | CL=15pF, See Figure 7 and Figure 8 | 6 | |
| Enable to Output High Time in Off State | tRPSH | 200 | 1400 | ns | CL=15pF, See Figure 7 and Figure 8 | 6 | |
| Enable to Output Low Time in Off State | tRPSL | 200 | 1400 | ns | CL=15pF, See Figure 7 and Figure 8 | 6 | |
| Time to shutdown | tSHDN | 80 | 300 | ns | NOTE2 | 6 | |
| Over Temperature Shutdown Threshold Temperature | 140 | ℃ | 4 | ||||
| Over-temperature shutdown hysteresis temperature | 20 | ℃ | 4 |
CAD (KiCad official)
- Symbol:
XD3485 - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
xd3485-etched.step/xd3485-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd3485.step/xd3485.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (14 pp, sha256
19e1b70d8514813f, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).