component
XD14053
Public Made by Adomby adom
XINLUDA Signal Switches, Multiplexers, Decoders, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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XD14053
XINLUDA · Signal Switches, Multiplexers, Decoders · DIP-16
XD14053 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | bidirectional | Independent switch terminal Y1 of the Y channel, connected to common Y (pin 15) when selected by input B, referenced to VEE. |
| 2 | Y0 | bidirectional | Independent switch terminal Y0 of the Y channel, connected to common Y (pin 15) when selected by input B, referenced to VEE. |
| 3 | Z1 | bidirectional | Independent switch terminal Z1 of the Z channel, connected to common Z (pin 4) when selected by input C, referenced to VEE. |
| 4 | Z | bidirectional | Common out/in terminal of the Z switch (SPDT between Z0 and Z1), referenced to VEE. |
| 5 | Z0 | bidirectional | Independent switch terminal Z0 of the Z channel, connected to common Z (pin 4) when selected by input C, referenced to VEE. |
| 6 | INH | input | Inhibit control input; logic 1 turns all switches off, referenced to VSS, with logic thresholds set by VDD and VSS. |
| 7 | VEE | power_in | Negative supply for the analog switch section; VEE must be at or below VSS, and VDD − VEE is 3.0 to 18 V. |
| 8 | VSS | power_in | Digital ground/logic-low reference for the control inputs; VSS must be at or above VEE. |
| 9 | C | input | Select control input C, which selects between Z0 and Z1, referenced to VSS. |
| 10 | B | input | Select control input B, which selects between Y0 and Y1, referenced to VSS. |
| 11 | A | input | Select control input A, which selects between X0 and X1, referenced to VSS. |
| 12 | X0 | bidirectional | Independent switch terminal X0 of the X channel, connected to common X (pin 14) when selected by input A, referenced to VEE. |
| 13 | X1 | bidirectional | Independent switch terminal X1 of the X channel, connected to common X (pin 14) when selected by input A, referenced to VEE. |
| 14 | X | bidirectional | Common out/in terminal of the X switch (SPDT between X0 and X1), referenced to VEE. |
| 15 | Y | bidirectional | Common out/in terminal of the Y switch (SPDT between Y0 and Y1), referenced to VEE. |
| 16 | VDD | power_in | Positive supply; supply range is 3.0 to 18 V and the absolute maximum is 18.0 V referenced to VEE. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage Range | VDD | 3 | 18 | V | Voltages referenced to VEE; all temperatures | 3 | |
| Quiescent Current Per Package (VDD 5.0 V) | IDD | 5 | µA | VDD=5.0 V, −40°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | ||
| Quiescent Current Per Package (VDD 10 V) | IDD | 10 | µA | VDD=10 V, −40°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | ||
| Quiescent Current Per Package (VDD 15 V) | IDD | 20 | µA | VDD=15 V, −40°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | ||
| Quiescent Current Per Package (VDD 5.0 V) | IDD | 0.005 | 5 | µA | VDD=5.0 V, 25°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | |
| Quiescent Current Per Package (VDD 10 V) | IDD | 0.01 | 10 | µA | VDD=10 V, 25°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | |
| Quiescent Current Per Package (VDD 15 V) | IDD | 0.015 | 20 | µA | VDD=15 V, 25°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | |
| Quiescent Current Per Package (VDD 5.0 V) | IDD | 150 | µA | VDD=5.0 V, 85°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | ||
| Quiescent Current Per Package (VDD 10 V) | IDD | 300 | µA | VDD=10 V, 85°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | ||
| Quiescent Current Per Package (VDD 15 V) | IDD | 600 | µA | VDD=15 V, 85°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 | ||
| Low-Level Input Voltage (VDD 5.0 V) | VIL | 1.5 | V | VDD=5.0 V, −40°C; Ron = per spec, Ioff = per spec | 3 | ||
| Low-Level Input Voltage (VDD 10 V) | VIL | 3 | V | VDD=10 V, −40°C; Ron = per spec, Ioff = per spec | 3 | ||
| Low-Level Input Voltage (VDD 15 V) | VIL | 4 | V | VDD=15 V, −40°C; Ron = per spec, Ioff = per spec | 3 | ||
| Low-Level Input Voltage (VDD 5.0 V) | VIL | 2.25 | 1.5 | V | VDD=5.0 V, 25°C; Ron = per spec, Ioff = per spec | 3 | |
| Low-Level Input Voltage (VDD 10 V) | VIL | 4.5 | 3 | V | VDD=10 V, 25°C; Ron = per spec, Ioff = per spec | 3 | |
| Low-Level Input Voltage (VDD 15 V) | VIL | 6.75 | 4 | V | VDD=15 V, 25°C; Ron = per spec, Ioff = per spec | 3 | |
| High-Level Input Voltage (VDD 5.0 V) | VIH | 3.5 | V | VDD=5.0 V, −40°C; Ron = per spec, Ioff = per spec | 3 | ||
| High-Level Input Voltage (VDD 10 V) | VIH | 7 | V | VDD=10 V, −40°C; Ron = per spec, Ioff = per spec | 3 | ||
| High-Level Input Voltage (VDD 15 V) | VIH | 11 | V | VDD=15 V, −40°C; Ron = per spec, Ioff = per spec | 3 | ||
| High-Level Input Voltage (VDD 5.0 V) | VIH | 3.5 | 2.75 | V | VDD=5.0 V, 25°C; Ron = per spec, Ioff = per spec | 3 | |
| High-Level Input Voltage (VDD 10 V) | VIH | 7 | 5.5 | V | VDD=10 V, 25°C; Ron = per spec, Ioff = per spec | 3 | |
| High-Level Input Voltage (VDD 15 V) | VIH | 11 | 8.25 | V | VDD=15 V, 25°C; Ron = per spec, Ioff = per spec | 3 | |
| ON Resistance (VDD 5.0 V) | Ron | 800 | Ω | VDD=5.0 V, −40°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | ||
| ON Resistance (VDD 10 V) | Ron | 400 | Ω | VDD=10 V, −40°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | ||
| ON Resistance (VDD 15 V) | Ron | 220 | Ω | VDD=15 V, −40°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | ||
| ON Resistance (VDD 5.0 V) | Ron | 250 | 1050 | Ω | VDD=5.0 V, 25°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | |
| ON Resistance (VDD 10 V) | Ron | 120 | 500 | Ω | VDD=10 V, 25°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | |
| ON Resistance (VDD 15 V) | Ron | 80 | 280 | Ω | VDD=15 V, 25°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | |
| ON Resistance (VDD 5.0 V) | Ron | 1200 | Ω | VDD=5.0 V, 85°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | ||
| ON Resistance (VDD 10 V) | Ron | 520 | Ω | VDD=10 V, 85°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | ||
| ON Resistance (VDD 15 V) | Ron | 300 | Ω | VDD=15 V, 85°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 | ||
| Input Leakage Current (15 V) | Iin | 0.1 | µA | VDD=15 V, −40°C; Vin = 0 or VDD − 0.1 | 3 | ||
| Input Leakage Current (15 V) | Iin | 1 | µA | VDD=15 V, 85°C; Vin = 0 or VDD − 0.1 | 3 | ||
| Input Capacitance | Cin | 5 | 7.5 | pF | 3 | ||
| Channel On Voltage Across Switch (ΔVswitch) | ΔVswitch | 0 | 600 | mV | Channel On; −40°C | 3 | |
| Channel On Voltage Across Switch (ΔVswitch) | ΔVswitch | 0 | 300 | mV | Channel On; 85°C | 3 | |
| Propagation Delay, Switch Input to Switch Output (VDD−VEE 5.0 V) | tPLH, tPHL | 25 | 65 | ns | RL = 1 kΩ, CL = 50 pF, TA = 25°C | 4 | |
| Propagation Delay, Switch Input to Switch Output (VDD−VEE 10 V) | tPLH, tPHL | 8 | 20 | ns | RL = 1 kΩ, CL = 50 pF, TA = 25°C | 4 | |
| Propagation Delay, Switch Input to Switch Output (VDD−VEE 15 V) | tPLH, tPHL | 6 | 15 | ns | RL = 1 kΩ, CL = 50 pF, TA = 25°C | 4 | |
| Inhibit to Output Disable/Enable Time (VDD−VEE 5.0 V) | tPHZ, tPLZ, tPZH, tPZL | 275 | 550 | ns | RL = 10 kΩ, VEE = VSS; output 1 or 0 to high impedance, or high impedance to 1 or 0 | 4 | |
| Inhibit to Output Disable/Enable Time (VDD−VEE 10 V) | tPHZ, tPLZ, tPZH, tPZL | 140 | 280 | ns | RL = 10 kΩ, VEE = VSS; output 1 or 0 to high impedance, or high impedance to 1 or 0 | 4 | |
| Inhibit to Output Disable/Enable Time (VDD−VEE 15 V) | tPHZ, tPLZ, tPZH, tPZL | 110 | 220 | ns | RL = 10 kΩ, VEE = VSS; output 1 or 0 to high impedance, or high impedance to 1 or 0 | 4 | |
| DC Supply Voltage Range (absolute maximum) | VDD | -0.5 | 18 | V | Referenced to VEE, VSS ≥ VEE | 2 | |
| Input or Output Voltage Range (absolute maximum) | Vin, Vout | -0.5 | V | DC or transient; referenced to VSS for control inputs and VEE for switch I/O; upper limit printed as VDD + 0.5 | 2 | ||
| Input Current per Control Pin (absolute maximum) | Iin | 10 | mA | DC or transient, per control pin | 2 | ||
| Switch Through Current (absolute maximum) | ISW | 25 | mA | 2 | |||
| Power Dissipation per Package (absolute maximum) | PD | 500 | mW | Per package (Note 1) | 2 | ||
| Ambient Temperature Range (absolute maximum) | TA | -40 | 85 | °C | 2 | ||
| Storage Temperature Range (absolute maximum) | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature (absolute maximum) | TL | 260 | °C | 8-second soldering | 2 | ||
| Recommended Maximum Difference VDD to VEE | VDD − VEE | 15 | V | Recommended maximum; most parameters specified up to 15 V | 9 |
CAD (KiCad official)
- Symbol:
XD14053 - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
xd14053-etched.step/xd14053-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd14053.step/xd14053.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (11 pp, sha256
ac3edc047eccbba4, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# XD14053
**XINLUDA** · Signal Switches, Multiplexers, Decoders · DIP-16
XD14053 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | bidirectional | Independent switch terminal Y1 of the Y channel, connected to common Y (pin 15) when selected by input B, referenced to VEE. |
| 2 | Y0 | bidirectional | Independent switch terminal Y0 of the Y channel, connected to common Y (pin 15) when selected by input B, referenced to VEE. |
| 3 | Z1 | bidirectional | Independent switch terminal Z1 of the Z channel, connected to common Z (pin 4) when selected by input C, referenced to VEE. |
| 4 | Z | bidirectional | Common out/in terminal of the Z switch (SPDT between Z0 and Z1), referenced to VEE. |
| 5 | Z0 | bidirectional | Independent switch terminal Z0 of the Z channel, connected to common Z (pin 4) when selected by input C, referenced to VEE. |
| 6 | INH | input | Inhibit control input; logic 1 turns all switches off, referenced to VSS, with logic thresholds set by VDD and VSS. |
| 7 | VEE | power_in | Negative supply for the analog switch section; VEE must be at or below VSS, and VDD − VEE is 3.0 to 18 V. |
| 8 | VSS | power_in | Digital ground/logic-low reference for the control inputs; VSS must be at or above VEE. |
| 9 | C | input | Select control input C, which selects between Z0 and Z1, referenced to VSS. |
| 10 | B | input | Select control input B, which selects between Y0 and Y1, referenced to VSS. |
| 11 | A | input | Select control input A, which selects between X0 and X1, referenced to VSS. |
| 12 | X0 | bidirectional | Independent switch terminal X0 of the X channel, connected to common X (pin 14) when selected by input A, referenced to VEE. |
| 13 | X1 | bidirectional | Independent switch terminal X1 of the X channel, connected to common X (pin 14) when selected by input A, referenced to VEE. |
| 14 | X | bidirectional | Common out/in terminal of the X switch (SPDT between X0 and X1), referenced to VEE. |
| 15 | Y | bidirectional | Common out/in terminal of the Y switch (SPDT between Y0 and Y1), referenced to VEE. |
| 16 | VDD | power_in | Positive supply; supply range is 3.0 to 18 V and the absolute maximum is 18.0 V referenced to VEE. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage Range | VDD | 3 | | 18 | V | Voltages referenced to VEE; all temperatures | 3 |
| Quiescent Current Per Package (VDD 5.0 V) | IDD | | | 5 | µA | VDD=5.0 V, −40°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Quiescent Current Per Package (VDD 10 V) | IDD | | | 10 | µA | VDD=10 V, −40°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Quiescent Current Per Package (VDD 15 V) | IDD | | | 20 | µA | VDD=15 V, −40°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Quiescent Current Per Package (VDD 5.0 V) | IDD | | 0.005 | 5 | µA | VDD=5.0 V, 25°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Quiescent Current Per Package (VDD 10 V) | IDD | | 0.01 | 10 | µA | VDD=10 V, 25°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Quiescent Current Per Package (VDD 15 V) | IDD | | 0.015 | 20 | µA | VDD=15 V, 25°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Quiescent Current Per Package (VDD 5.0 V) | IDD | | | 150 | µA | VDD=5.0 V, 85°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Quiescent Current Per Package (VDD 10 V) | IDD | | | 300 | µA | VDD=10 V, 85°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Quiescent Current Per Package (VDD 15 V) | IDD | | | 600 | µA | VDD=15 V, 85°C; Vin=VSS or VDD; VEE≤VI/O≤VDD; ΔVswitch≤500 mV | 3 |
| Low-Level Input Voltage (VDD 5.0 V) | VIL | | | 1.5 | V | VDD=5.0 V, −40°C; Ron = per spec, Ioff = per spec | 3 |
| Low-Level Input Voltage (VDD 10 V) | VIL | | | 3 | V | VDD=10 V, −40°C; Ron = per spec, Ioff = per spec | 3 |
| Low-Level Input Voltage (VDD 15 V) | VIL | | | 4 | V | VDD=15 V, −40°C; Ron = per spec, Ioff = per spec | 3 |
| Low-Level Input Voltage (VDD 5.0 V) | VIL | | 2.25 | 1.5 | V | VDD=5.0 V, 25°C; Ron = per spec, Ioff = per spec | 3 |
| Low-Level Input Voltage (VDD 10 V) | VIL | | 4.5 | 3 | V | VDD=10 V, 25°C; Ron = per spec, Ioff = per spec | 3 |
| Low-Level Input Voltage (VDD 15 V) | VIL | | 6.75 | 4 | V | VDD=15 V, 25°C; Ron = per spec, Ioff = per spec | 3 |
| High-Level Input Voltage (VDD 5.0 V) | VIH | 3.5 | | | V | VDD=5.0 V, −40°C; Ron = per spec, Ioff = per spec | 3 |
| High-Level Input Voltage (VDD 10 V) | VIH | 7 | | | V | VDD=10 V, −40°C; Ron = per spec, Ioff = per spec | 3 |
| High-Level Input Voltage (VDD 15 V) | VIH | 11 | | | V | VDD=15 V, −40°C; Ron = per spec, Ioff = per spec | 3 |
| High-Level Input Voltage (VDD 5.0 V) | VIH | 3.5 | 2.75 | | V | VDD=5.0 V, 25°C; Ron = per spec, Ioff = per spec | 3 |
| High-Level Input Voltage (VDD 10 V) | VIH | 7 | 5.5 | | V | VDD=10 V, 25°C; Ron = per spec, Ioff = per spec | 3 |
| High-Level Input Voltage (VDD 15 V) | VIH | 11 | 8.25 | | V | VDD=15 V, 25°C; Ron = per spec, Ioff = per spec | 3 |
| ON Resistance (VDD 5.0 V) | Ron | | | 800 | Ω | VDD=5.0 V, −40°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| ON Resistance (VDD 10 V) | Ron | | | 400 | Ω | VDD=10 V, −40°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| ON Resistance (VDD 15 V) | Ron | | | 220 | Ω | VDD=15 V, −40°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| ON Resistance (VDD 5.0 V) | Ron | | 250 | 1050 | Ω | VDD=5.0 V, 25°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| ON Resistance (VDD 10 V) | Ron | | 120 | 500 | Ω | VDD=10 V, 25°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| ON Resistance (VDD 15 V) | Ron | | 80 | 280 | Ω | VDD=15 V, 25°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| ON Resistance (VDD 5.0 V) | Ron | | | 1200 | Ω | VDD=5.0 V, 85°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| ON Resistance (VDD 10 V) | Ron | | | 520 | Ω | VDD=10 V, 85°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| ON Resistance (VDD 15 V) | Ron | | | 300 | Ω | VDD=15 V, 85°C; ΔVswitch ≤ 500 mV; Vin = VIL or VIH (control), Vin = 0 to VDD (switch) | 3 |
| Input Leakage Current (15 V) | Iin | | | 0.1 | µA | VDD=15 V, −40°C; Vin = 0 or VDD − 0.1 | 3 |
| Input Leakage Current (15 V) | Iin | | | 1 | µA | VDD=15 V, 85°C; Vin = 0 or VDD − 0.1 | 3 |
| Input Capacitance | Cin | | 5 | 7.5 | pF | | 3 |
| Channel On Voltage Across Switch (ΔVswitch) | ΔVswitch | 0 | | 600 | mV | Channel On; −40°C | 3 |
| Channel On Voltage Across Switch (ΔVswitch) | ΔVswitch | 0 | | 300 | mV | Channel On; 85°C | 3 |
| Propagation Delay, Switch Input to Switch Output (VDD−VEE 5.0 V) | tPLH, tPHL | | 25 | 65 | ns | RL = 1 kΩ, CL = 50 pF, TA = 25°C | 4 |
| Propagation Delay, Switch Input to Switch Output (VDD−VEE 10 V) | tPLH, tPHL | | 8 | 20 | ns | RL = 1 kΩ, CL = 50 pF, TA = 25°C | 4 |
| Propagation Delay, Switch Input to Switch Output (VDD−VEE 15 V) | tPLH, tPHL | | 6 | 15 | ns | RL = 1 kΩ, CL = 50 pF, TA = 25°C | 4 |
| Inhibit to Output Disable/Enable Time (VDD−VEE 5.0 V) | tPHZ, tPLZ, tPZH, tPZL | | 275 | 550 | ns | RL = 10 kΩ, VEE = VSS; output 1 or 0 to high impedance, or high impedance to 1 or 0 | 4 |
| Inhibit to Output Disable/Enable Time (VDD−VEE 10 V) | tPHZ, tPLZ, tPZH, tPZL | | 140 | 280 | ns | RL = 10 kΩ, VEE = VSS; output 1 or 0 to high impedance, or high impedance to 1 or 0 | 4 |
| Inhibit to Output Disable/Enable Time (VDD−VEE 15 V) | tPHZ, tPLZ, tPZH, tPZL | | 110 | 220 | ns | RL = 10 kΩ, VEE = VSS; output 1 or 0 to high impedance, or high impedance to 1 or 0 | 4 |
| DC Supply Voltage Range (absolute maximum) | VDD | -0.5 | | 18 | V | Referenced to VEE, VSS ≥ VEE | 2 |
| Input or Output Voltage Range (absolute maximum) | Vin, Vout | -0.5 | | | V | DC or transient; referenced to VSS for control inputs and VEE for switch I/O; upper limit printed as VDD + 0.5 | 2 |
| Input Current per Control Pin (absolute maximum) | Iin | | | 10 | mA | DC or transient, per control pin | 2 |
| Switch Through Current (absolute maximum) | ISW | | | 25 | mA | | 2 |
| Power Dissipation per Package (absolute maximum) | PD | | | 500 | mW | Per package (Note 1) | 2 |
| Ambient Temperature Range (absolute maximum) | TA | -40 | | 85 | °C | | 2 |
| Storage Temperature Range (absolute maximum) | Tstg | -65 | | 150 | °C | | 2 |
| Lead Temperature (absolute maximum) | TL | | | 260 | °C | 8-second soldering | 2 |
| Recommended Maximum Difference VDD to VEE | VDD − VEE | | | 15 | V | Recommended maximum; most parameters specified up to 15 V | 9 |
## CAD (KiCad official)
- Symbol: `XD14053`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `xd14053-etched.step` / `xd14053-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xd14053.step` / `xd14053.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XINLUDA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588894408272330752) (11 pp, sha256 `ac3edc047eccbba4`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/xd14053-datasheet.pdf)