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XD14051

Public Made by Adom

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XINLUDA Signal Switches, Multiplexers, Decoders, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD14051

XINLUDA · Signal Switches, Multiplexers, Decoders · DIP-16

XD14051 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 X4 bidirectional Analog switch X4 input/output (channel 4 of the 8-channel multiplexer), referenced to VEE.
2 X6 bidirectional Analog switch X6 input/output (channel 6), referenced to VEE.
3 X bidirectional Common output/input of the multiplexer, connected to the selected channel X0-X7.
4 X7 bidirectional Analog switch X7 input/output (channel 7), referenced to VEE.
5 X5 bidirectional Analog switch X5 input/output (channel 5), referenced to VEE.
6 INH input Inhibit control input referenced to VSS; high turns all switches off (no channel selected).
7 VEE power_in Negative supply for analog signals; VEE must be ≤ VSS and VDD − VEE is 3.0 to 18 V.
8 VSS power_in Digital ground/logic-low reference for the control inputs; must be ≥ VEE.
9 C input Channel select input C (MSB), referenced to VSS.
10 B input Channel select input B, referenced to VSS.
11 A input Channel select input A (LSB), referenced to VSS.
12 X3 bidirectional Analog switch X3 input/output (channel 3), referenced to VEE.
13 X0 bidirectional Analog switch X0 input/output (channel 0), referenced to VEE.
14 X1 bidirectional Analog switch X1 input/output (channel 1), referenced to VEE.
15 X2 bidirectional Analog switch X2 input/output (channel 2), referenced to VEE.
16 VDD power_in Positive supply voltage, 3.0 to 18 V referenced to VEE (absolute maximum 18.0 V).

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Range (VDD referenced to VEE) VDD -0.5 18 V Referenced to VEE 2
Input or Output Voltage Range, DC or transient (max printed as VDD + 0.5 V, not numeric) Vin, Vout -0.5 V Referenced to VSS for control inputs and VEE for switch I/O 2
Input Current per control pin (DC or transient) Iin 10 mA Per control pin 2
Switch Through Current ISW 25 mA 2
Power Dissipation per Package PD 500 mW Note 1 2
Ambient Temperature Range TA -40 85 °C 2
Storage Temperature Range Tstg -65 150 °C 2
Lead Temperature TL 260 °C 8-second soldering 2
Recommended maximum difference between VDD and VEE VDD − VEE 15 V Most parameters specified up to this value 9
Recommended peak-to-peak voltage into or out of the switch (max printed as VDD, not numeric) VI/O 0 VPP Channel on or off 3
Voltage drop across switch, channel on, -40°C ΔVswitch 0 600 mV Channel on; -40°C 3
Voltage drop across switch, channel on, 85°C ΔVswitch 0 300 mV Channel on; 85°C 3
Power Supply Voltage Range VDD 3 18 V Referenced to VEE 3
Quiescent Current per package, VDD = 5.0 V, -40°C max IDD 5 µA Vin = VSS or VDD; VEE ≤ VI/O ≤ VDD; ΔVswitch ≤ 500 mV (Note 3) 3
Quiescent Current per package, VDD = 10 V, -40°C max IDD 10 µA Vin = VSS or VDD; VEE ≤ VI/O ≤ VDD; ΔVswitch ≤ 500 mV (Note 3) 3
Quiescent Current per package, VDD = 15 V, -40°C max IDD 20 µA Vin = VSS or VDD; VEE ≤ VI/O ≤ VDD; ΔVswitch ≤ 500 mV (Note 3) 3
Quiescent Current per package, VDD = 5.0 V, 85°C max IDD 150 µA Vin = VSS or VDD; VEE ≤ VI/O ≤ VDD; ΔVswitch ≤ 500 mV (Note 3) 3
Quiescent Current per package, VDD = 10 V, 85°C max IDD 300 µA Vin = VSS or VDD; VEE ≤ VI/O ≤ VDD; ΔVswitch ≤ 500 mV (Note 3) 3
Quiescent Current per package, VDD = 15 V, 85°C max IDD 600 µA Vin = VSS or VDD; VEE ≤ VI/O ≤ VDD; ΔVswitch ≤ 500 mV (Note 3) 3
Low-Level Input Voltage, VDD = 5.0 V, -40°C max VIL 1.5 V Ron = per spec, Ioff = per spec 3
Low-Level Input Voltage, VDD = 10 V, -40°C max VIL 3 V Ron = per spec, Ioff = per spec 3
Low-Level Input Voltage, VDD = 15 V, -40°C max VIL 4 V Ron = per spec, Ioff = per spec 3
Low-Level Input Voltage, VDD = 5.0 V, 85°C max VIL 1.5 V Ron = per spec, Ioff = per spec 3
Low-Level Input Voltage, VDD = 10 V, 85°C max VIL 3 V Ron = per spec, Ioff = per spec 3
Low-Level Input Voltage, VDD = 15 V, 85°C max VIL 4 V Ron = per spec, Ioff = per spec 3
High-Level Input Voltage, VDD = 5.0 V, -40°C min VIH 3.5 V Ron = per spec, Ioff = per spec 3
High-Level Input Voltage, VDD = 10 V, -40°C min VIH 7 V Ron = per spec, Ioff = per spec 3
High-Level Input Voltage, VDD = 15 V, -40°C min VIH 11 V Ron = per spec, Ioff = per spec 3
High-Level Input Voltage, VDD = 5.0 V, 85°C min VIH 3.5 V Ron = per spec, Ioff = per spec 3
High-Level Input Voltage, VDD = 10 V, 85°C min VIH 7 V Ron = per spec, Ioff = per spec 3
High-Level Input Voltage, VDD = 15 V, 85°C min VIH 11 V Ron = per spec, Ioff = per spec 3
Input Leakage Current, VDD = 15 V, -40°C max Iin 0.1 µA Vin = 0 or VDD − 0.1 3
Input Leakage Current, VDD = 15 V, 85°C max Iin 1 µA Vin = 0 or VDD − 0.1 3
Input Capacitance Cin 5 7.5 pF 3
ON Resistance, VDD = 5.0 V, -40°C max Ron 800 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ON Resistance, VDD = 10 V, -40°C max Ron 400 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ON Resistance, VDD = 15 V, -40°C max Ron 220 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ON Resistance, VDD = 5.0 V, 25°C max Ron 1050 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ON Resistance, VDD = 10 V, 25°C max Ron 500 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ON Resistance, VDD = 15 V, 25°C max Ron 280 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ON Resistance, VDD = 5.0 V, 85°C max Ron 1200 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ON Resistance, VDD = 10 V, 85°C max Ron 520 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ON Resistance, VDD = 15 V, 85°C max Ron 300 Ω ΔVswitch ≤ 500 mV (Note 3); Vin = VIL or VIH (control), 0 to VDD (switch) 3
ΔON Resistance between any two channels, VDD = 5.0 V, -40°C max ΔRon 70 Ω Any two channels in the same package 3
ΔON Resistance between any two channels, VDD = 10 V, -40°C max ΔRon 50 Ω Any two channels in the same package 3
ΔON Resistance between any two channels, VDD = 15 V, -40°C max ΔRon 45 Ω Any two channels in the same package 3
ΔON Resistance between any two channels, VDD = 5.0 V, 85°C max ΔRon 135 Ω Any two channels in the same package 3
ΔON Resistance between any two channels, VDD = 10 V, 85°C max ΔRon 95 Ω Any two channels in the same package 3
ΔON Resistance between any two channels, VDD = 15 V, 85°C max ΔRon 65 Ω Any two channels in the same package 3
Propagation delay switch input to switch output, MC14051, VDD = 5.0 V tPLH, tPHL 35 90 ns CL = 50 pF; VEE ≤ VSS; RL = 1 kΩ 4
Propagation delay switch input to switch output, MC14051, VDD = 10 V tPLH, tPHL 15 40 ns CL = 50 pF; VEE ≤ VSS; RL = 1 kΩ 4
Propagation delay switch input to switch output, MC14051, VDD = 15 V tPLH, tPHL 12 30 ns CL = 50 pF; VEE ≤ VSS; RL = 1 kΩ 4
Inhibit to output high-Z transition, XL/XD14051, VDD = 5.0 V tPHZ, tPLZ, tPZH, tPZL 350 700 ns RL = 10 kΩ, VEE = VSS 4
Inhibit to output high-Z transition, XL/XD14051, VDD = 10 V tPHZ, tPLZ, tPZH, tPZL 170 340 ns RL = 10 kΩ, VEE = VSS 4
Inhibit to output high-Z transition, XL/XD14051, VDD = 15 V tPHZ, tPLZ, tPZH, tPZL 140 280 ns RL = 10 kΩ, VEE = VSS 4
Control input to output, XL/XD14051, VDD = 5.0 V tPLH, tPHL 360 720 ns RL = 1 kΩ, VEE = VSS 4
Control input to output, XL/XD14051, VDD = 10 V tPLH, tPHL 160 320 ns RL = 1 kΩ, VEE = VSS 4
Control input to output, XL/XD14051, VDD = 15 V tPLH, tPHL 120 240 ns RL = 1 kΩ, VEE = VSS 4

CAD (KiCad official)

  • Symbol: XD14051
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd14051-etched.step / xd14051-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd14051.step / xd14051.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (11 pp, sha256 ac3edc047eccbba4, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF