component
XD0832CC
Public Made by Adomby adom
XINLUDA Analog To Digital Converters (ADC), DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXD0832CC
XINLUDA · Analog To Digital Converters (ADC) · DIP-8
XD0832CC from XINLUDA, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select, active low: it must be held low for the whole conversion, and driving it high ends the process and disables the chip. |
| 2 | CH0 | input | Analog input channel 0, usable as IN+ or IN- depending on the multiplexer configuration (single-ended or differential). |
| 3 | CH1 | input | Analog input channel 1, usable as IN+ or IN- depending on the multiplexer configuration (single-ended or differential). |
| 4 | GND | power_in | Ground reference for the device; the ICs maximum VCC-to-GND rating is -0.5 V to 6.5 V and digital and analog pins are limited to VCC+0.3 V relative to GND. |
| 5 | DI | input | Data input for the channel-select/configuration bits (start bit, then single-ended or differential and polarity bits), sampled on each CLK rising edge; the pin is high-impedance during conversion. |
| 6 | DO | tri_state | Serial data output for the 8-bit conversion result (MSB first, then a second read LSB first); it is high-impedance when CS is high. |
| 7 | CLK | input | Serial clock input; the datasheet specifies a working frequency of 10 kHz to 400 kHz and a clock duty cycle of 40% to 60%. |
| 8 | VCC/REF | power_in | Power supply input (4.5 V minimum, 5.0 V typical per the electrical characteristics) that also serves as the reference voltage input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | DIP-8 |
| Category | Data Acquisition |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply (VCC) | VCC | 4.5 | V | 3 | |||
| Supply Current | ICC | 2 | mA | 3 | |||
| Logical "1" Input Voltage (Min) | VIH | 2 | V | VCC=5.25V | 3 | ||
| Logical "0" Input Voltage (Max) | VIL | 0.8 | V | VCC=4.75V | 3 | ||
| Logical "1" Input Current (Max) | IIH | 10 | µA | VIN=5.0V | 3 | ||
| Logical "0" Input Current (Max) | IIL | -10 | µA | VIN=0V | 3 | ||
| Logical "1" Output Voltage (Min) | VOH | 2.4 | V | VCC=4.75V, IOUT=−360 µA | 3 | ||
| Logical "1" Output Voltage (Min) | VOH | 4.5 | V | VCC=4.75V, IOUT=−10 µA | 3 | ||
| Logical "0" Output Voltage (Max) | VOL | 0.4 | V | VCC=4.75V, IOUT=1.6mA | 3 | ||
| Output Source Current (Min) | ISOURCE | -6.5 | mA | VOUT=0V | 3 | ||
| Output Sink Current (Min) | ISINK | 8 | mA | VOUT=VCC | 3 | ||
| Working Clock Frequency | fCLK | 10 | 400 | kHz | 3 | ||
| Conversion Time | tC | 8 | 1/fCLK | Not including MUX Addressing Time | 3 | ||
| Clock Duty Cycle | 40 | 60 | % | 3 | |||
| Data Input Valid after CLK Rising Edge | tHOLD | 200 | ns | 3 | |||
| CLK Falling Edge to Output Data Valid (MSB First) | tpd1 | 2000 | ns | CL=100 pF; Data MSB First | 3 | ||
| CLK Falling Edge to Output Data Valid (LSB First) | tpd0 | 1000 | ns | CL=100 pF; Data LSB First | 3 | ||
| Rising Edge of CS to Data Output and SAR Hi-Z | t1H,t0H | 400 | ns | CL=10 pF, RL=10k | 3 | ||
| VCC end to GND voltage | -0.5 | 6.5 | V | 2 | |||
| Storage temperature | -65 | 150 | ℃ | 2 | |||
| Operating ambient temperature | -20 | 85 | ℃ | 2 | |||
| Welding temperature (10 seconds) | 260 | ℃ | 10 seconds | 2 | |||
| Maximum junction temperature | 150 | ℃ | 2 | ||||
| Diffusion power dissipation | 0.8 | W | 2 | ||||
| ESD (HBM) withstand voltage | 4 | KV | HBM | 2 |
CAD (KiCad official)
- Symbol:
XD0832CC - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
xd0832cc-etched.step/xd0832cc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xd0832cc.step/xd0832cc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (7 pp, sha256
87c7ef837612e9ba, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).