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docs xc6210b332mr-g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json xc6210b332mr-g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 23h ago
README.md xc6210b332mr-g: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
xc6210b332mr-g-etched.fit.json xc6210b332mr-g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xc6210b332mr-g-etched.glb xc6210b332mr-g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xc6210b332mr-g-etched.step xc6210b332mr-g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xc6210b332mr-g.glb Publish 0.1.0 · Ray 1mo ago
xc6210b332mr-g.kicad_mod Publish 0.1.0 · Ray 1mo ago
xc6210b332mr-g.kicad_sym Publish 0.1.0 · Ray 1mo ago
xc6210b332mr-g.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 5 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
xc6210b332mr-g.step Publish 0.1.0 · Ray 1mo ago

XC6210B332MR-G

Torex Semicon · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-25-5

XC6210B332MR-G from Torex Semicon, in a SOT-25-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Unregulated input supply. Operating range 1.5 V to 6.0 V (absolute max 6.5 V). Connect a >=1.0 uF ceramic input capacitor (CIN) between VIN and VSS as close to the pin as possible.
2 VSS power_in Device ground / negative supply return. All internal references and the output regulation loop are referred to this node.
3 CE input Chip Enable (ON/OFF control). For the 'B' type this input is high-active with NO internal pull-down: VCE >= 1.3 V (up to 6.0 V) turns the regulator ON, VCE <= 0.25 V turns it OFF. Leaving CE OPEN gives an undefined state - tie to VIN or VSS.
4 NC unconnected No internal connection on the SOT-25 package. Leave floating or tie to VSS for mechanical stability.
5 VOUT power_out Regulated LDO output. Factory-trimmed to 3.30 V for the '332' option, ±2 % accuracy, up to 700 mA guaranteed (800 mA typ. current limit with foldback short-circuit protection ~50 mA). Requires a >=1.0 uF low-ESR ceramic output capacitor (CL) to VSS for phase compensation and stability.

Key specifications

Parameter Value
Manufacturer Torex Semicon
Package SOT-25-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • XC6210B332MR-G
  • XC6210B332MR-GPR
  • XC6210B332MR-GPR-G
  • XC6210B332MR-GDR
  • XC6210B332MR-GDR-G

CAD (KiCad official)

  • Symbol: XC6210B332MR-G
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-25-5 (KiCad packages3D, STEP)
  • 3D model files: xc6210b332mr-g-etched.step / xc6210b332mr-g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xc6210b332mr-g.step / xc6210b332mr-g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Torex Semicon datasheet (27 pp, sha256 c83318855bc5eab7, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF