component

XC6206P502MR

Public Made by Adom

by adom

Torex Semicon Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs xc6206p502mr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json xc6206p502mr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md xc6206p502mr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
xc6206p502mr-etched.fit.json xc6206p502mr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
xc6206p502mr-etched.glb xc6206p502mr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
xc6206p502mr-etched.step xc6206p502mr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
xc6206p502mr.glb Publish 0.1.0 · Ray
xc6206p502mr.kicad_mod Publish 0.1.0 · Ray
xc6206p502mr.kicad_sym Publish 0.1.0 · Ray
xc6206p502mr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
xc6206p502mr.step Publish 0.1.0 · Ray

XC6206P502MR

Torex Semicon · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L

XC6206P502MR from Torex Semicon, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSS power_in Ground reference pin. Common return for VIN and VOUT; connect to system ground.
2 VOUT power_out Regulated 5.0V output pin (±2% accuracy, VOUT(T)=5.0V). Sources up to 200mA (typical); requires a ~1.0 µF ceramic capacitor (CL) to VSS for stability and low ESR compatibility.
3 VIN power_in Unregulated input supply pin. Operating range 1.8V to 6.0V (absolute max 7.0V); requires a ~1.0 µF ceramic input capacitor (CIN) to VSS for stability.

Key specifications

Parameter Value
Manufacturer Torex Semicon
Package SOT-23-3L
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • XC6206P502MR
  • XC6206P502MR-G
  • XC6206P502MRPR
  • XC6206P502MRPR-G
  • XC6206P502MRDR
  • XC6206P502MRDR-G
  • XC6206P502MRTH
  • XC6206P502MRTH-G
  • XC6206P502MRTB
  • XC6206P502MRTB-G

CAD (KiCad official)

  • Symbol: XC6206P502MR
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3L (KiCad packages3D, STEP)
  • 3D model files: xc6206p502mr-etched.step / xc6206p502mr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xc6206p502mr.step / xc6206p502mr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
xc6206p502mr.step 59 KB You want the bare part, or you mark your own boards.
xc6206p502mr-etched.step 2.5 MB You want the part with XC6206P502MR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 579 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Torex Semicon datasheet (17 pp, sha256 8fda1e40ea3e7c17, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF