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docs xc6201p332mr-g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json xc6201p332mr-g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1d ago
README.md xc6201p332mr-g: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
xc6201p332mr-g-etched.fit.json xc6201p332mr-g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xc6201p332mr-g-etched.glb xc6201p332mr-g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xc6201p332mr-g-etched.step xc6201p332mr-g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
xc6201p332mr-g.glb Publish 0.1.0 · Ray 1mo ago
xc6201p332mr-g.kicad_mod Publish 0.1.0 · Ray 1mo ago
xc6201p332mr-g.kicad_sym Publish 0.1.0 · Ray 1mo ago
xc6201p332mr-g.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 5 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
xc6201p332mr-g.step Publish 0.1.0 · Ray 1mo ago

XC6201P332MR-G

Torex Semicon · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-25

XC6201P332MR-G from Torex Semicon, in a SOT-25. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Power input. Accepts up to 10V maximum operating voltage. Recommended 1.0μF tantalum or ceramic input capacitor to VSS.
2 VSS power_in Device ground / common return for the internal error amplifier, reference, and pass transistor.
3 NC unconnected No internal connection. Leave floating or tie to ground per PCB convenience.
4 NC unconnected No internal connection. Leave floating or tie to ground per PCB convenience.
5 VOUT power_out Regulated 3.3V output (±2% accuracy for the '2' suffix). Delivers 250mA typical with 0.16V dropout at 100mA. Requires 1.0μF tantalum or ceramic output capacitor to VSS for stability.

Key specifications

Parameter Value
Manufacturer Torex Semicon
Package SOT-25
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • XC6201P332MR-G
  • XC6201P332MR-GML
  • XC6201P332MR-GPR
  • XC6201P332MR-GPL
  • XC6201P332MR-GTR
  • XC6201P332MR-GTH
  • XC6201P332MR-GTB
  • XC6201P332MR-GLR
  • XC6201P332MR-GLH
  • XC6201P332MR-GLB

CAD (KiCad official)

  • Symbol: XC6201P332MR-G
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-25 (KiCad packages3D, STEP)
  • 3D model files: xc6201p332mr-g-etched.step / xc6201p332mr-g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xc6201p332mr-g.step / xc6201p332mr-g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Torex Semicon datasheet (22 pp, sha256 b2988f855a4e8c02, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF