component

XC3S50AN-4TQG144C

Public Made by Adom

by adom

XILINX CPLD/FPGA, TQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersxc3s50an-4tqg144cfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

XC3S50AN-4TQG144C

XILINX · CPLD/FPGA · TQFP-144(20x20)

XC3S50AN-4TQG144C from XILINX, in a TQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TMS input Dedicated JTAG test mode select pin, powered by VCCAUX.
2 TDI input Dedicated JTAG test data input pin, powered by VCCAUX.
3 IO_L02P_3 bidirectional Bank 3 user I/O, differential pair 02 positive.
4 IO_L01P_3 bidirectional Bank 3 user I/O, differential pair 01 positive.
5 IO_L02N_3 bidirectional Bank 3 user I/O, differential pair 02 negative.
6 IO_L01N_3 bidirectional Bank 3 user I/O, differential pair 01 negative.
7 IO_L03P_3 bidirectional Bank 3 user I/O, differential pair 03 positive.
8 IO_L03N_3 bidirectional Bank 3 user I/O, differential pair 03 negative.
9 GND power_in Dedicated ground pin; all GND pins must be connected.
10 IO_L04P_3 bidirectional Bank 3 user I/O, differential pair 04 positive.
11 IO_L04N_3/VREF_3 bidirectional Bank 3 user I/O or reference voltage input for bank 3 (all VREF_3 pins must be connected if used).
12 IO_L05P_3/LHCLK0 bidirectional Bank 3 user I/O or left-half clock input LHCLK0.
13 IO_L05N_3/LHCLK1 bidirectional Bank 3 user I/O or left-half clock input LHCLK1.
14 VCCO_3 power_in Output voltage supply for I/O bank 3; sets input threshold for some I/O standards.
15 IO_L06P_3/LHCLK2 bidirectional Bank 3 user I/O or left-half clock input LHCLK2.
16 IO_L06N_3/IRDY2/LHCLK3 bidirectional Bank 3 user I/O, PCI IRDY2 or left-half clock input LHCLK3.
17 GND power_in Dedicated ground pin; all GND pins must be connected.
18 IO_L07P_3/LHCLK4 bidirectional Bank 3 user I/O or left-half clock input LHCLK4.
19 IO_L08P_3/TRDY2/LHCLK6 bidirectional Bank 3 user I/O, PCI TRDY2 or left-half clock input LHCLK6.
20 IO_L07N_3/LHCLK5 bidirectional Bank 3 user I/O or left-half clock input LHCLK5.
21 IO_L08N_3/LHCLK7 bidirectional Bank 3 user I/O or left-half clock input LHCLK7.
22 VCCINT power_in Internal core logic supply, must be connected to +1.2V.
23 VCCO_3 power_in Output voltage supply for I/O bank 3; sets input threshold for some I/O standards.
24 IO_L09P_3 bidirectional Bank 3 user I/O, differential pair 09 positive.
25 IO_L09N_3 bidirectional Bank 3 user I/O, differential pair 09 negative.
26 GND power_in Dedicated ground pin; all GND pins must be connected.
27 IO_L10P_3 bidirectional Bank 3 user I/O, differential pair 10 positive.
28 IO_L11P_3 bidirectional Bank 3 user I/O, differential pair 11 positive.
29 IO_L10N_3 bidirectional Bank 3 user I/O, differential pair 10 negative.
30 IO_L11N_3 bidirectional Bank 3 user I/O, differential pair 11 negative.
31 IO_L12P_3 bidirectional Bank 3 user I/O, differential pair 12 positive.
32 IO_L12N_3 bidirectional Bank 3 user I/O, differential pair 12 negative.
33 IP_L13P_3 input Bank 3 input-only pin with no output structure, differential pair 13 positive.
34 GND power_in Dedicated ground pin; all GND pins must be connected.
35 IP_L13N_3/VREF_3 input Bank 3 input-only pin or reference voltage input for bank 3.
36 VCCAUX power_in Auxiliary supply, must be connected to +3.3V; also powers the in-system Flash.
37 IO_L01P_2/M1 bidirectional Dual-purpose configuration mode select M1, then user I/O in bank 2.
38 IO_L01N_2/M0 bidirectional Dual-purpose configuration mode select M0, then user I/O in bank 2.
39 IO_L02P_2/M2 bidirectional Dual-purpose configuration mode select M2, then user I/O in bank 2.
40 VCCO_2 power_in Output voltage supply for I/O bank 2; sets input threshold for some I/O standards.
41 IO_L02N_2/CSO_B bidirectional Dual-purpose configuration chip-select output CSO_B, then user I/O in bank 2.
42 IO_L03P_2/RDWR_B bidirectional Dual-purpose Slave Parallel read/write control RDWR_B, then user I/O in bank 2.
43 IO_L04P_2/VS2 bidirectional Dual-purpose variant select VS2, then user I/O in bank 2.
44 IO_L03N_2/VS1 bidirectional Dual-purpose variant select VS1, then user I/O in bank 2.
45 IO_L04N_2/VS0 bidirectional Dual-purpose variant select VS0, then user I/O in bank 2.
46 IO_L05P_2 bidirectional Bank 2 user I/O, differential pair 05 positive.
47 IO_L06P_2 bidirectional Bank 2 user I/O, differential pair 06 positive.
48 IO_L05N_2/D7 bidirectional Dual-purpose configuration data bit D7, then user I/O in bank 2.
49 IO_L06N_2/D6 bidirectional Dual-purpose configuration data bit D6, then user I/O in bank 2.
50 IO_L07P_2/D5 bidirectional Dual-purpose configuration data bit D5, then user I/O in bank 2.
51 IO_L07N_2/D4 bidirectional Dual-purpose configuration data bit D4, then user I/O in bank 2.
52 VCCINT power_in Internal core logic supply, must be connected to +1.2V.
53 IP_2/VREF_2 input Bank 2 input-only pin or reference voltage input for bank 2.
54 IO_L08P_2/GCLK14 bidirectional Bank 2 user I/O or global clock input GCLK14.
55 IO_L08N_2/GCLK15 bidirectional Bank 2 user I/O or global clock input GCLK15.
56 GND power_in Dedicated ground pin; all GND pins must be connected.
57 IO_L09P_2/GCLK0 bidirectional Bank 2 user I/O or global clock input GCLK0.
58 IO_L10P_2/GCLK2 bidirectional Bank 2 user I/O or global clock input GCLK2.
59 IO_L09N_2/GCLK1 bidirectional Bank 2 user I/O or global clock input GCLK1.
60 IO_L10N_2/GCLK3 bidirectional Bank 2 user I/O or global clock input GCLK3.
61 VCCO_2 power_in Output voltage supply for I/O bank 2; sets input threshold for some I/O standards.
62 IO_2/MOSI/CSI_B bidirectional Dual-purpose SPI MOSI / Slave Parallel chip select CSI_B, then user I/O in bank 2.
63 IO_L11P_2/AWAKE bidirectional Suspend-mode status pin AWAKE; usable as user I/O unless Suspend mode is enabled.
64 IO_L11N_2/DOUT bidirectional Dual-purpose serial configuration data output DOUT, then user I/O in bank 2.
65 GND power_in Dedicated ground pin; all GND pins must be connected.
66 VCCAUX power_in Auxiliary supply, must be connected to +3.3V; also powers the in-system Flash.
67 IO_L12P_2/INIT_B bidirectional Dual-purpose configuration initialization INIT_B, then user I/O in bank 2.
68 IO_L12N_2/D3 bidirectional Dual-purpose configuration data bit D3, then user I/O in bank 2.
69 IO_L13P_2/D2 bidirectional Dual-purpose configuration data bit D2, then user I/O in bank 2.
70 IO_L14P_2/D1 bidirectional Dual-purpose configuration data bit D1, then user I/O in bank 2.
71 IO_L13N_2/D0/DIN/MISO bidirectional Dual-purpose configuration data D0/DIN/MISO, then user I/O in bank 2.
72 IO_L14N_2/CCLK bidirectional Dual-purpose configuration clock CCLK, then user I/O in bank 2.
73 DONE bidirectional Dedicated configuration pin indicating configuration is finished, powered by VCCAUX.
74 SUSPEND input Dedicated Suspend mode control pin, powered by VCCAUX.
75 IO_L02P_1/LDC1 bidirectional Dual-purpose configuration pin LDC1, then user I/O in bank 1.
76 IO_L01P_1/HDC bidirectional Dual-purpose configuration pin HDC, then user I/O in bank 1.
77 IO_L02N_1/LDC0 bidirectional Dual-purpose configuration pin LDC0, then user I/O in bank 1.
78 IO_L01N_1/LDC2 bidirectional Dual-purpose configuration pin LDC2, then user I/O in bank 1.
79 IO_1 bidirectional Bank 1 unrestricted general-purpose user I/O.
80 IP_1/VREF_1 input Bank 1 input-only pin or reference voltage input for bank 1.
81 GND power_in Dedicated ground pin; all GND pins must be connected.
82 IO_L03P_1 bidirectional Bank 1 user I/O, differential pair 03 positive.
83 IO_L04P_1/RHCLK0 bidirectional Bank 1 user I/O or right-half clock input RHCLK0.
84 IO_L03N_1 bidirectional Bank 1 user I/O, differential pair 03 negative.
85 IO_L04N_1/RHCLK1 bidirectional Bank 1 user I/O or right-half clock input RHCLK1.
86 VCCO_1 power_in Output voltage supply for I/O bank 1; sets input threshold for some I/O standards.
87 IO_L05P_1/RHCLK2 bidirectional Bank 1 user I/O or right-half clock input RHCLK2.
88 IO_L05N_1/TRDY1/RHCLK3 bidirectional Bank 1 user I/O, PCI TRDY1 or right-half clock input RHCLK3.
89 GND power_in Dedicated ground pin; all GND pins must be connected.
90 IO_L06P_1/RHCLK4 bidirectional Bank 1 user I/O or right-half clock input RHCLK4.
91 IO_L07P_1/IRDY1/RHCLK6 bidirectional Bank 1 user I/O, PCI IRDY1 or right-half clock input RHCLK6.
92 IO_L06N_1/RHCLK5 bidirectional Bank 1 user I/O or right-half clock input RHCLK5.
93 IO_L07N_1/RHCLK7 bidirectional Bank 1 user I/O or right-half clock input RHCLK7.
94 VCCINT power_in Internal core logic supply, must be connected to +1.2V.
95 VCCO_1 power_in Output voltage supply for I/O bank 1; sets input threshold for some I/O standards.
96 IO_L08P_1 bidirectional Bank 1 user I/O, differential pair 08 positive.
97 IP_1/VREF_1 input Bank 1 input-only pin or reference voltage input for bank 1.
98 IO_L08N_1 bidirectional Bank 1 user I/O, differential pair 08 negative.
99 IO_L09P_1 bidirectional Bank 1 user I/O, differential pair 09 positive.
100 GND power_in Dedicated ground pin; all GND pins must be connected.
101 IO_L09N_1 bidirectional Bank 1 user I/O, differential pair 09 negative.
102 IO_L10P_1 bidirectional Bank 1 user I/O, differential pair 10 positive.
103 IO_L11P_1 bidirectional Bank 1 user I/O, differential pair 11 positive.
104 IO_L10N_1 bidirectional Bank 1 user I/O, differential pair 10 negative.
105 IO_L11N_1 bidirectional Bank 1 user I/O, differential pair 11 negative.
106 GND power_in Dedicated ground pin; all GND pins must be connected.
107 TDO output Dedicated JTAG test data output pin, powered by VCCAUX.
108 VCCAUX power_in Auxiliary supply, must be connected to +3.3V; also powers the in-system Flash.
109 TCK input Dedicated JTAG test clock pin, powered by VCCAUX.
110 IO_L01P_0 bidirectional Bank 0 user I/O, differential pair 01 positive.
111 IO_L01N_0 bidirectional Bank 0 user I/O, differential pair 01 negative.
112 IO_L02P_0/VREF_0 bidirectional Bank 0 user I/O or reference voltage input for bank 0.
113 IO_L02N_0 bidirectional Bank 0 user I/O, differential pair 02 negative.
114 IO_L04P_0 bidirectional Bank 0 user I/O, differential pair 04 positive.
115 IO_L03P_0 bidirectional Bank 0 user I/O, differential pair 03 positive.
116 IO_L04N_0 bidirectional Bank 0 user I/O, differential pair 04 negative.
117 IO_L03N_0 bidirectional Bank 0 user I/O, differential pair 03 negative.
118 GND power_in Dedicated ground pin; all GND pins must be connected.
119 VCCO_0 power_in Output voltage supply for I/O bank 0; sets input threshold for some I/O standards.
120 IO_L05P_0 bidirectional Bank 0 user I/O, differential pair 05 positive.
121 IO_L05N_0 bidirectional Bank 0 user I/O, differential pair 05 negative.
122 VCCINT power_in Internal core logic supply, must be connected to +1.2V.
123 IP_0/VREF_0 input Bank 0 input-only pin or reference voltage input for bank 0.
124 IO_L06P_0/GCLK4 bidirectional Bank 0 user I/O or global clock input GCLK4.
125 IO_L07P_0/GCLK6 bidirectional Bank 0 user I/O or global clock input GCLK6.
126 IO_L06N_0/GCLK5 bidirectional Bank 0 user I/O or global clock input GCLK5.
127 IO_L07N_0/GCLK7 bidirectional Bank 0 user I/O or global clock input GCLK7.
128 GND power_in Dedicated ground pin; all GND pins must be connected.
129 IO_L08P_0/GCLK8 bidirectional Bank 0 user I/O or global clock input GCLK8.
130 IO_L09P_0/GCLK10 bidirectional Bank 0 user I/O or global clock input GCLK10.
131 IO_L08N_0/GCLK9 bidirectional Bank 0 user I/O or global clock input GCLK9.
132 IO_L09N_0/GCLK11 bidirectional Bank 0 user I/O or global clock input GCLK11.
133 VCCAUX power_in Auxiliary supply, must be connected to +3.3V; also powers the in-system Flash.
134 IO_L10P_0 bidirectional Bank 0 user I/O, differential pair 10 positive.
135 IO_L10N_0 bidirectional Bank 0 user I/O, differential pair 10 negative.
136 VCCO_0 power_in Output voltage supply for I/O bank 0; sets input threshold for some I/O standards.
137 GND power_in Dedicated ground pin; all GND pins must be connected.
138 IO_L11P_0 bidirectional Bank 0 user I/O, differential pair 11 positive.
139 IO_L11N_0 bidirectional Bank 0 user I/O, differential pair 11 negative.
140 IP_0 input Bank 0 unrestricted general-purpose input-only pin.
141 IO_L12P_0/VREF_0 bidirectional Bank 0 user I/O or reference voltage input for bank 0.
142 IO_0 bidirectional Bank 0 unrestricted general-purpose user I/O.
143 IO_L12N_0/PUDC_B bidirectional Dual-purpose pull-up during configuration control PUDC_B, then user I/O in bank 0.
144 PROG_B input Dedicated configuration pin that initiates (re)configuration, powered by VCCAUX.

Key specifications

Parameter Value
Manufacturer XILINX
Package TQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal supply voltage VCCINT -0.5 1.32 V 12
Auxiliary supply voltage VCCAUX -0.5 3.75 V 12
Output driver supply voltage VCCO -0.5 3.75 V 12
Voltage applied to all User I/O pins and dual-purpose pins VIN -0.95 4.6 V Driver in a high-impedance state 12
Voltage applied to all Dedicated pins VIN -0.5 4.6 V 12
Input clamp current per I/O pin IIK 100 mA -0.5V < VIN < (VCCO + 0.5V); printed as ±100 12
ESD voltage, human body model VESD -2000 2000 V Human body model 12
ESD voltage, charged device model VESD -500 500 V Charged device model 12
ESD voltage, machine model VESD -200 200 V Machine model 12
Junction temperature TJ 125 °C 12
Storage temperature TSTG -65 150 °C 12
Junction temperature, Commercial TJ 0 85 °C Commercial 14
Internal supply voltage VCCINT 1.14 1.2 1.26 V 14
Output driver supply voltage VCCO 1.1 3.6 V 14
Auxiliary supply voltage VCCAUX 3 3.3 3.6 V VCCAUX = 3.3V 14
Input voltage, PCI IOSTANDARD VIN -0.5 V PCI IOSTANDARD; max printed as VCCO + 0.5 14
Input voltage, all other IOSTANDARDs VIN -0.5 4.1 V All other IOSTANDARDs, IP or IO_# and IO_Lxxy_# 14
Input signal transition time TIN 500 ns 14
Threshold for VCCINT supply VCCINTT 0.4 1 V 13
Threshold for VCCAUX supply VCCAUXT 1 2 V 13
Threshold for VCCO Bank 2 supply VCCO2T 1 2 V 13
Ramp rate GND to valid VCCINT VCCINTR 0.2 100 ms 13
Ramp rate GND to valid VCCAUX VCCAUXR 0.2 100 ms 13
VCCINT level to retain CCL and RAM data VDRINT 1 V 13
VCCAUX level to retain CCL and RAM data VDRAUX 2 V 13
Leakage current at User I/O, Input-only, Dual-Purpose and Dedicated pins IL -10 10 µA Driver is in a high-impedance state, VIN = 0V or VCCO max, sample-tested 15
Leakage current during hot socketing IHS -10 10 µA All pins except INIT_B, PROG_B, DONE, and JTAG pins when PUDC_B = 1 15
Pull-up current IRPU -151 -315 -710 µA VIN = GND, VCCO or VCCAUX = 3.0V to 3.6V 15
Equivalent pull-up resistor RPU 5.1 11.4 23.9 kΩ VIN = GND, VCCO = 3.0V to 3.6V 15
Pull-down current IRPD 167 346 659 µA VIN = VCCO, VCCAUX = 3.0V to 3.6V 15
Equivalent pull-down resistor RPD 5.5 10.4 20.8 kΩ VCCAUX = 3.0V to 3.6V, VIN = 3.0V to 3.6V 15
VREF current per pin IREF -10 10 µA All VCCO levels 15
Input capacitance CIN 10 pF 15
Differential termination resistance RDT 90 100 115 Ω VCCO = 3.3V ± 10% LVDS_33, MINI_LVDS_33, RSDS_33 15
Quiescent VCCINT supply current ICCINTQ 2 20 mA XC3S50AN, Commercial maximum 16
Quiescent VCCO supply current ICCOQ 0.2 2 mA XC3S50AN, Commercial maximum 16
Quiescent VCCAUX supply current ICCAUXQ 3.1 8.1 mA XC3S50AN, Commercial maximum 16
Clock-to-output time with DCM, -4 TICKOFDCM 3.42 ns LVCMOS25, 12 mA output drive, Fast slew rate, with DCM, XC3S50AN 25
Clock-to-output time without DCM, -4 TICKOF 5.02 ns LVCMOS25, 12 mA output drive, Fast slew rate, without DCM, XC3S50AN 25
Setup time with DCM, -4 TPSDCM 2.68 ns LVCMOS25, IFD_DELAY_VALUE = 0, with DCM, XC3S50AN 26
Setup time without DCM, -4 TPSFD 2.76 ns LVCMOS25, IFD_DELAY_VALUE = 5, without DCM, XC3S50AN 26
Hold time with DCM, -4 TPHDCM -0.36 ns LVCMOS25, IFD_DELAY_VALUE = 0, with DCM, XC3S50AN 26
Hold time without DCM, -4 TPHFD -0.58 ns LVCMOS25, IFD_DELAY_VALUE = 5, without DCM, XC3S50AN 26
IOB input propagation time, no delay, -4 TIOPI 1.12 ns LVCMOS25, IBUF_DELAY_VALUE=0, XC3S50AN 30
IOB output clock-to-output, -4 TIOCKP 3.13 ns LVCMOS25, 12 mA output drive, Fast slew rate 36
IOB output propagation, -4 TIOOP 2.91 ns LVCMOS25, 12 mA output drive, Fast slew rate 36
CLB clock-to-output, -4 TCKO 0.68 ns 47
CLB LUT propagation, -4 TILO 0.71 ns 47
CLB toggle frequency, -4 FTOG 0 667 MHz 47

CAD (KiCad official)

  • Symbol: XC3S50AN-4TQG144C
  • Footprint: Package_QFP:TQFP-144_20x20mm_P0.5mm
  • 3D model: TQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: xc3s50an-4tqg144c-etched.step / xc3s50an-4tqg144c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xc3s50an-4tqg144c.step / xc3s50an-4tqg144c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XILINX datasheet (123 pp, sha256 4dea04fc9a722b3e, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF