XC3S500E-4PQG208C

@@ -0,0 +1,272 @@+# XC3S500E-4PQG208C++**AMD XILINX** · Programmable Logic Device (CPLDs/FPGAs) · PQFP-208++XC3S500E-4PQG208C from AMD XILINX, in a PQFP-208. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PROG_B | input | Active-Low program input; asserting it Low for 500 ns or longer restarts configuration, and an external 4.7 kΩ pull-up to 2.5V is recommended. |+| 2 | IO_L01P_3 | bidirectional | Differential pair L01 true-line general-purpose user I/O in Bank 3. |+| 3 | IO_L01N_3 | bidirectional | Differential pair L01 inverted-line general-purpose user I/O in Bank 3. |+| 4 | IO_L02P_3 | bidirectional | Differential pair L02 true-line general-purpose user I/O in Bank 3. |+| 5 | IO_L02N_3/VREF_3 | bidirectional | Differential pair L02 inverted-line user I/O that serves as a VREF input for Bank 3; all VREF pins in the bank must be connected if used as a reference. |+| 6 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 7 | VCCAUX | power_in | Auxiliary supply pin that must be connected to +2.5V. |+| 8 | IO_L03P_3 | bidirectional | Differential pair L03 true-line general-purpose user I/O in Bank 3. |+| 9 | IO_L03N_3 | bidirectional | Differential pair L03 inverted-line general-purpose user I/O in Bank 3. |+| 10 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 11 | IO_L04P_3 | bidirectional | Differential pair L04 true-line general-purpose user I/O in Bank 3. |+| 12 | IO_L04N_3 | bidirectional | Differential pair L04 inverted-line general-purpose user I/O in Bank 3. |+| 13 | VCCINT | power_in | Internal core logic supply pin that must be connected to +1.2V. |+| 14 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 15 | IO_L05P_3 | bidirectional | Differential pair L05 true-line general-purpose user I/O in Bank 3. |+| 16 | IO_L05N_3 | bidirectional | Differential pair L05 inverted-line general-purpose user I/O in Bank 3. |+| 17 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 18 | IO_L06P_3 | bidirectional | Differential pair L06 true-line general-purpose user I/O in Bank 3. |+| 19 | IO_L06N_3 | bidirectional | Differential pair L06 inverted-line general-purpose user I/O in Bank 3. |+| 20 | IP/VREF_3 | input | Input-only pin that is also a VREF input for Bank 3; all VREF pins in the bank must be connected if a reference voltage is used. |+| 21 | VCCO_3 | power_in | Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage. |+| 22 | IO_L07P_3/LHCLK0 | bidirectional | Left-half clock input LHCLK0 that is also a differential true-line user I/O in Bank 3. |+| 23 | IO_L07N_3/LHCLK1 | bidirectional | Left-half clock input LHCLK1 that is also a differential inverted-line user I/O in Bank 3. |+| 24 | IO_L08P_3/LHCLK2 | bidirectional | Left-half clock input LHCLK2 that is also a differential true-line user I/O in Bank 3. |+| 25 | IO_L08N_3/LHCLK3 | bidirectional | Left-half clock input LHCLK3 that is also a differential inverted-line user I/O in Bank 3. |+| 26 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 27 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 28 | IO_L09P_3/LHCLK4 | bidirectional | Left-half clock input LHCLK4 that is also a differential true-line user I/O in Bank 3. |+| 29 | IO_L09N_3/LHCLK5 | bidirectional | Left-half clock input LHCLK5 that is also a differential inverted-line user I/O in Bank 3. |+| 30 | IO_L10P_3/LHCLK6 | bidirectional | Left-half clock input LHCLK6 that is also a differential true-line user I/O in Bank 3. |+| 31 | IO_L10N_3/LHCLK7 | bidirectional | Left-half clock input LHCLK7 that is also a differential inverted-line user I/O in Bank 3. |+| 32 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 33 | IO_L11P_3 | bidirectional | Differential pair L11 true-line general-purpose user I/O in Bank 3. |+| 34 | IO_L11N_3 | bidirectional | Differential pair L11 inverted-line general-purpose user I/O in Bank 3. |+| 35 | IO_L12P_3 | bidirectional | Differential pair L12 true-line general-purpose user I/O in Bank 3. |+| 36 | IO_L12N_3 | bidirectional | Differential pair L12 inverted-line general-purpose user I/O in Bank 3. |+| 37 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 38 | VCCO_3 | power_in | Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage. |+| 39 | IO_L13P_3 | bidirectional | Differential pair L13 true-line general-purpose user I/O in Bank 3. |+| 40 | IO_L13N_3 | bidirectional | Differential pair L13 inverted-line general-purpose user I/O in Bank 3. |+| 41 | IO_L14P_3 | bidirectional | Differential pair L14 true-line general-purpose user I/O in Bank 3. |+| 42 | IO_L14N_3 | bidirectional | Differential pair L14 inverted-line general-purpose user I/O in Bank 3. |+| 43 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 44 | VCCAUX | power_in | Auxiliary supply pin that must be connected to +2.5V. |+| 45 | IO/VREF_3 | bidirectional | General-purpose user I/O that is also a VREF reference input for Bank 3; all VREF pins in the bank must be connected if used. |+| 46 | VCCO_3 | power_in | Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage. |+| 47 | IO_L15P_3 | bidirectional | Differential pair L15 true-line general-purpose user I/O in Bank 3. |+| 48 | IO_L15N_3 | bidirectional | Differential pair L15 inverted-line general-purpose user I/O in Bank 3. |+| 49 | IO_L16P_3 | bidirectional | Differential pair L16 true-line general-purpose user I/O in Bank 3. |+| 50 | IO_L16N_3 | bidirectional | Differential pair L16 inverted-line general-purpose user I/O in Bank 3. |+| 51 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 52 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 53 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 54 | IP | input | Input-only pin in Bank 2 with no output structure, differential termination resistor, or PCI clamp diode. |+| 55 | IO_L01P_2/CSO_B | bidirectional | Dual-purpose CSO_B chip-select output (Active Low) during configuration, then a user I/O after configuration. |+| 56 | IO_L01N_2/INIT_B | bidirectional | Open-drain INIT_B initialization indicator (Active Low) during configuration; drive High if unused as user I/O. |+| 57 | IP_L02P_2 | input | Input-only true-line pin of differential pair L02 in Bank 2; on-chip differential termination is not available on dedicated inputs. |+| 58 | IP_L02N_2 | input | Input-only inverted-line pin of differential pair L02 in Bank 2; on-chip differential termination is not available on dedicated inputs. |+| 59 | VCCO_2 | power_in | Output-buffer supply for Bank 2, which must match the configuration source voltage and is an input to the Power-On Reset circuit. |+| 60 | IO_L03P_2/DOUT/BUSY | bidirectional | Dual-purpose DOUT/BUSY pin that drives daisy-chain serial data or BUSY status during configuration, then is a user I/O. |+| 61 | IO_L03N_2/MOSI/CSI_B | bidirectional | Dual-purpose MOSI (SPI) or CSI_B chip-select input (must be Low throughout parallel configuration), then a user I/O. |+| 62 | IO_L04P_2 | bidirectional | General-purpose user I/O, differential pair L04 true line in Bank 2. |+| 63 | IO_L04N_2 | bidirectional | General-purpose user I/O, differential pair L04 inverted line in Bank 2. |+| 64 | IO_L05P_2 | bidirectional | General-purpose user I/O, differential pair L05 true line in Bank 2. |+| 65 | IO_L05N_2 | bidirectional | General-purpose user I/O, differential pair L05 inverted line in Bank 2. |+| 66 | VCCAUX | power_in | Auxiliary supply pin that must be connected to +2.5V. |+| 67 | VCCINT | power_in | Internal core logic supply pin that must be connected to +1.2V. |+| 68 | IO_L06P_2 | bidirectional | General-purpose user I/O, differential pair L06 true line in Bank 2. |+| 69 | IO_L06N_2 | bidirectional | General-purpose user I/O, differential pair L06 inverted line in Bank 2. |+| 70 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 71 | IP_L07P_2 | input | Input-only true-line pin of differential pair L07 in Bank 2. |+| 72 | IP_L07N_2/VREF_2 | input | Input-only inverted-line pin that is also a VREF input for Bank 2; all VREF pins in the bank must be connected if used. |+| 73 | VCCO_2 | power_in | Output-buffer supply for Bank 2; all VCCO pins of the bank must be connected to the same voltage. |+| 74 | IO_L08P_2/D7/GCLK12 | bidirectional | Dual-purpose D7 configuration data bit and global clock input GCLK12, usable as user I/O after configuration. |+| 75 | IO_L08N_2/D6/GCLK13 | bidirectional | Dual-purpose D6 configuration data bit and global clock input GCLK13, usable as user I/O after configuration. |+| 76 | IO/D5 | bidirectional | Dual-purpose D5 configuration data bit used in parallel modes, then a user I/O. |+| 77 | IO_L09P_2/D4/GCLK14 | bidirectional | Dual-purpose D4 configuration data bit and global clock input GCLK14, usable as user I/O after configuration. |+| 78 | IO_L09N_2/D3/GCLK15 | bidirectional | Dual-purpose D3 configuration data bit and global clock input GCLK15, usable as user I/O after configuration. |+| 79 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 80 | IP_L10P_2/RDWR_B/GCLK0 | bidirectional | Dual-purpose RDWR_B read/write control (must be Low during configuration) and global clock input GCLK0. |+| 81 | IP_L10N_2/M2/GCLK1 | bidirectional | Dual-purpose M2 mode-select pin sampled when INIT_B goes High, shared with global clock input GCLK1 (design note: avoid using GCLK1 as a clock). |+| 82 | IO_L11P_2/D2/GCLK2 | bidirectional | Dual-purpose D2 configuration data bit and global clock input GCLK2, usable as user I/O after configuration. |+| 83 | IO_L11N_2/D1/GCLK3 | bidirectional | Dual-purpose D1 configuration data bit and global clock input GCLK3, usable as user I/O after configuration. |+| 84 | IO/M1 | input | Dual-purpose M1 mode-select pin that must be at a defined level when INIT_B goes High, then a user I/O. |+| 85 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 86 | IO_L12P_2/M0 | input | Dual-purpose M0 mode-select pin that must be at a defined level when INIT_B goes High, then a user I/O. |+| 87 | IO_L12N_2/DIN/D0 | input | Dual-purpose DIN/D0 serial configuration data input, then a user I/O after configuration. |+| 88 | VCCO_2 | power_in | Output-buffer supply for Bank 2; all VCCO pins of the bank must be connected to the same voltage. |+| 89 | IO_L13P_2 | bidirectional | General-purpose user I/O, differential pair L13 true line in Bank 2. |+| 90 | IO_L13N_2 | bidirectional | General-purpose user I/O, differential pair L13 inverted line in Bank 2. |+| 91 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 92 | VCCAUX | power_in | Auxiliary supply pin that must be connected to +2.5V. |+| 93 | IO_L14P_2/A23 | bidirectional | Dual-purpose BPI address line A23 used in parallel Flash configuration, then a user I/O. |+| 94 | IO_L14N_2/A22 | bidirectional | Dual-purpose BPI address line A22 used in parallel Flash configuration, then a user I/O. |+| 95 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 96 | IO_L15P_2/A21 | bidirectional | Dual-purpose BPI address line A21 used in parallel Flash configuration, then a user I/O. |+| 97 | IO_L15N_2/A20 | bidirectional | Dual-purpose BPI address line A20 used in parallel Flash configuration, then a user I/O. |+| 98 | IO/VREF_2 | bidirectional | General-purpose user I/O that is also a VREF input for Bank 2; all VREF pins in the bank must be connected if used. |+| 99 | IO_L16P_2/VS2/A19 | bidirectional | Dual-purpose SPI variant-select VS2 (sampled when INIT_B goes High) and BPI address line A19, then a user I/O. |+| 100 | IO_L16N_2/VS1/A18 | bidirectional | Dual-purpose SPI variant-select VS1 (sampled when INIT_B goes High) and BPI address line A18, then a user I/O. |+| 101 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 102 | IO_L17P_2/VS0/A17 | bidirectional | Dual-purpose SPI variant-select VS0 (sampled when INIT_B goes High) and BPI address line A17, then a user I/O. |+| 103 | IO_L17N_2/CCLK | bidirectional | Dual-purpose configuration clock CCLK, driven by the FPGA in master modes and an input in slave modes, then a user I/O. |+| 104 | DONE | bidirectional | Open-drain configuration DONE indicator that goes High when configuration completes and requires an external 330 Ω pull-up to 2.5V. |+| 105 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 106 | IO_L01P_1/A16 | bidirectional | Dual-purpose BPI address line A16 used in parallel Flash configuration, then a user I/O (differential pair L01 true line). |+| 107 | IO_L01N_1/A15 | bidirectional | Dual-purpose BPI address line A15 used in parallel Flash configuration, then a user I/O (differential pair L01 inverted line). |+| 108 | IO_L02P_1/A14 | bidirectional | Dual-purpose BPI address line A14 used in parallel Flash configuration, then a user I/O (differential pair L02 true line). |+| 109 | IO_L02N_1/A13 | bidirectional | Dual-purpose BPI address line A13 used in parallel Flash configuration, then a user I/O (differential pair L02 inverted line). |+| 110 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 111 | VCCAUX | power_in | Auxiliary supply pin that must be connected to +2.5V. |+| 112 | IO_L03P_1 | bidirectional | General-purpose user I/O, differential pair L03 true line in Bank 1. |+| 113 | IO_L03N_1/VREF_1 | bidirectional | Differential pair L03 inverted-line user I/O that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used. |+| 114 | VCCO_1 | power_in | Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage. |+| 115 | IO_L04P_1 | bidirectional | General-purpose user I/O, differential pair L04 true line in Bank 1. |+| 116 | IO_L04N_1 | bidirectional | General-purpose user I/O, differential pair L04 inverted line in Bank 1. |+| 117 | VCCINT | power_in | Internal core logic supply pin that must be connected to +1.2V. |+| 118 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 119 | IO_L05P_1/A12 | bidirectional | Dual-purpose BPI address line A12 used in parallel Flash configuration, then a user I/O (differential pair L05 true line). |+| 120 | IO_L05N_1/A11 | bidirectional | Dual-purpose BPI address line A11 used in parallel Flash configuration, then a user I/O (differential pair L05 inverted line). |+| 121 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 122 | IO_L06P_1 | bidirectional | General-purpose user I/O, differential pair L06 true line in Bank 1. |+| 123 | IO_L06N_1/VREF_1 | bidirectional | Differential pair L06 inverted-line user I/O that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used. |+| 124 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 125 | VCCO_1 | power_in | Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage. |+| 126 | IO_L07P_1/A10/RHCLK0 | bidirectional | Right-half clock input RHCLK0 and dual-purpose BPI address line A10, then a user I/O. |+| 127 | IO_L07N_1/A9/RHCLK1 | bidirectional | Right-half clock input RHCLK1 and dual-purpose BPI address line A9, then a user I/O. |+| 128 | IO_L08P_1/A8/RHCLK2 | bidirectional | Right-half clock input RHCLK2 and dual-purpose BPI address line A8, then a user I/O. |+| 129 | IO_L08N_1/A7/RHCLK3 | bidirectional | Right-half clock input RHCLK3 and dual-purpose BPI address line A7, then a user I/O. |+| 130 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 131 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 132 | IO_L09P_1/A6/RHCLK4 | bidirectional | Right-half clock input RHCLK4 and dual-purpose BPI address line A6, then a user I/O. |+| 133 | IO_L09N_1/A5/RHCLK5 | bidirectional | Right-half clock input RHCLK5 and dual-purpose BPI address line A5, then a user I/O. |+| 134 | IO_L10P_1/A4/RHCLK6 | bidirectional | Right-half clock input RHCLK6 and dual-purpose BPI address line A4, then a user I/O. |+| 135 | IO_L10N_1/A3/RHCLK7 | bidirectional | Right-half clock input RHCLK7 and dual-purpose BPI address line A3, then a user I/O. |+| 136 | IP/VREF_1 | input | Input-only pin that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used. |+| 137 | IO_L11P_1/A2 | bidirectional | Dual-purpose BPI address line A2 used in parallel Flash configuration, then a user I/O (differential pair L11 true line). |+| 138 | IO_L11N_1/A1 | bidirectional | Dual-purpose BPI address line A1 used in parallel Flash configuration, then a user I/O (differential pair L11 inverted line). |+| 139 | IO_L12P_1 | bidirectional | General-purpose user I/O, differential pair L12 true line in Bank 1. |+| 140 | IO_L12N_1/A0 | bidirectional | Dual-purpose BPI address line A0 used in parallel Flash configuration, then a user I/O (differential pair L12 inverted line). |+| 141 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 142 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 143 | VCCO_1 | power_in | Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage. |+| 144 | IO_L13P_1 | bidirectional | General-purpose user I/O, differential pair L13 true line in Bank 1. |+| 145 | IO_L13N_1 | bidirectional | General-purpose user I/O, differential pair L13 inverted line in Bank 1. |+| 146 | IO_L14P_1 | bidirectional | General-purpose user I/O, differential pair L14 true line in Bank 1. |+| 147 | IO_L14N_1 | bidirectional | General-purpose user I/O, differential pair L14 inverted line in Bank 1. |+| 148 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 149 | VCCAUX | power_in | Auxiliary supply pin that must be connected to +2.5V. |+| 150 | IO_L15P_1/HDC | bidirectional | Dual-purpose HDC parallel Flash write-enable (WE#) output during configuration, then a user I/O. |+| 151 | IO_L15N_1/LDC0 | bidirectional | Dual-purpose LDC0 parallel Flash chip-enable (CE#) output driven Low during configuration, then a user I/O. |+| 152 | IO_L16P_1/LDC1 | bidirectional | Dual-purpose LDC1 parallel Flash output-enable (OE#) driven Low during configuration, then a user I/O. |+| 153 | IO_L16N_1/LDC2 | bidirectional | Dual-purpose LDC2 parallel Flash BYTE# control, driven Low during configuration, then a user I/O. |+| 154 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 155 | TMS | input | Dedicated JTAG test mode select input, powered by VCCAUX. |+| 156 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 157 | TDO | output | Dedicated JTAG test data output, powered by VCCAUX. |+| 158 | TCK | input | Dedicated JTAG test clock input, powered by VCCAUX. |+| 159 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 160 | IO_L01P_0 | bidirectional | General-purpose user I/O, differential pair L01 true line in Bank 0. |+| 161 | IO_L01N_0 | bidirectional | General-purpose user I/O, differential pair L01 inverted line in Bank 0. |+| 162 | IO_L02P_0 | bidirectional | General-purpose user I/O, differential pair L02 true line in Bank 0. |+| 163 | IO_L02N_0/VREF_0 | bidirectional | Differential pair L02 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used. |+| 164 | IO_L03P_0 | bidirectional | General-purpose user I/O, differential pair L03 true line in Bank 0. |+| 165 | IO_L03N_0 | bidirectional | General-purpose user I/O, differential pair L03 inverted line in Bank 0. |+| 166 | VCCAUX | power_in | Auxiliary supply pin that must be connected to +2.5V. |+| 167 | IO_L04P_0 | bidirectional | General-purpose user I/O, differential pair L04 true line in Bank 0. |+| 168 | IO_L04N_0/VREF_0 | bidirectional | Differential pair L04 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used. |+| 169 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 170 | VCCINT | power_in | Internal core logic supply pin that must be connected to +1.2V. |+| 171 | IO_L05P_0 | bidirectional | General-purpose user I/O, differential pair L05 true line in Bank 0. |+| 172 | IO_L05N_0 | bidirectional | General-purpose user I/O, differential pair L05 inverted line in Bank 0. |+| 173 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 174 | IP_L06P_0 | input | Input-only true-line pin of differential pair L06 in Bank 0 with no output structure or differential termination. |+| 175 | IP_L06N_0 | input | Input-only inverted-line pin of differential pair L06 in Bank 0 with no output structure or differential termination. |+| 176 | VCCO_0 | power_in | Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage. |+| 177 | IO_L07P_0/GCLK4 | bidirectional | Global clock input GCLK4 that is also a differential true-line user I/O in Bank 0. |+| 178 | IO_L07N_0/GCLK5 | bidirectional | Global clock input GCLK5 that is also a differential inverted-line user I/O in Bank 0. |+| 179 | IO/VREF_0 | bidirectional | General-purpose user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used. |+| 180 | IO_L08P_0/GCLK6 | bidirectional | Global clock input GCLK6 that is also a differential true-line user I/O in Bank 0. |+| 181 | IO_L08N_0/GCLK7 | bidirectional | Global clock input GCLK7 that is also a differential inverted-line user I/O in Bank 0. |+| 182 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 183 | IP_L09P_0/GCLK8 | bidirectional | Global clock input GCLK8 that is also a differential true-line pin in Bank 0. |+| 184 | IP_L09N_0/GCLK9 | bidirectional | Global clock input GCLK9 that is also a differential inverted-line pin in Bank 0. |+| 185 | IO_L10P_0/GCLK10 | bidirectional | Global clock input GCLK10 that is also a differential true-line user I/O in Bank 0. |+| 186 | IO_L10N_0/GCLK11 | bidirectional | Global clock input GCLK11 that is also a differential inverted-line user I/O in Bank 0. |+| 187 | IO | bidirectional | Unrestricted general-purpose user I/O in Bank 0. |+| 188 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 189 | IO_L11P_0 | bidirectional | General-purpose user I/O, differential pair L11 true line in Bank 0. |+| 190 | IO_L11N_0 | bidirectional | General-purpose user I/O, differential pair L11 inverted line in Bank 0. |+| 191 | VCCO_0 | power_in | Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage. |+| 192 | IO_L12P_0 | bidirectional | General-purpose user I/O, differential pair L12 true line in Bank 0. |+| 193 | IO_L12N_0/VREF_0 | bidirectional | Differential pair L12 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used. |+| 194 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 195 | VCCAUX | power_in | Auxiliary supply pin that must be connected to +2.5V. |+| 196 | IO_L13P_0 | bidirectional | General-purpose user I/O, differential pair L13 true line in Bank 0. |+| 197 | IO_L13N_0 | bidirectional | General-purpose user I/O, differential pair L13 inverted line in Bank 0. |+| 198 | GND | power_in | Ground return pin; all GND pins must be connected. |+| 199 | IO_L14P_0 | bidirectional | General-purpose user I/O, differential pair L14 true line in Bank 0. |+| 200 | IO_L14N_0/VREF_0 | bidirectional | Differential pair L14 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used. |+| 201 | VCCO_0 | power_in | Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage. |+| 202 | IO_L15P_0 | bidirectional | General-purpose user I/O, differential pair L15 true line in Bank 0. |+| 203 | IO_L15N_0 | bidirectional | General-purpose user I/O, differential pair L15 inverted line in Bank 0. |+| 204 | IP | input | Input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |+| 205 | IO_L16P_0 | bidirectional | General-purpose user I/O, differential pair L16 true line in Bank 0. |+| 206 | IO_L16N_0/HSWAP | bidirectional | Dual-purpose HSWAP pin: Low enables pull-up resistors on all user I/O during configuration, High disables them; then a user I/O. |+| 207 | TDI | input | Dedicated JTAG test data input, powered by VCCAUX. |+| 208 | GND | power_in | Ground return pin; all GND pins must be connected. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | AMD XILINX |+| Package | PQFP-208 |+| Category | Embedded Processors & Controllers |+| Pins | 208 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Operating temperature range (TJ), Commercial grade | TJ | 0 |  | 85 | °C | Commercial (C) grade, as in ordering information | 6 |+| Clock-to-output time, with DCM (TICKOFDCM), XC3S500E -4 | TICKOFDCM |  |  | 3.46 | ns | LVCMOS25, 12 mA output drive, Fast slew rate, with DCM | 125 |+| Clock-to-output time, without DCM (TICKOF), XC3S500E -4 | TICKOF |  |  | 5.51 | ns | LVCMOS25, 12 mA output drive, Fast slew rate, without DCM | 125 |+| Setup time to IFF with DCM (TPSDCM), XC3S500E -4 | TPSDCM | 2.59 |  |  | ns | LVCMOS25, IFD_DELAY_VALUE = 0, with DCM | 126 |+| Setup time to IFF without DCM (TPSFD), XC3S500E -4 | TPSFD | 4.73 |  |  | ns | LVCMOS25, IFD_DELAY_VALUE = default software setting (delay value 3) | 126 |+| Hold time to IFF with DCM (TPHDCM), XC3S500E -4 | TPHDCM | 0.14 |  |  | ns | LVCMOS25, IFD_DELAY_VALUE = 0, with DCM | 126 |+| Hold time to IFF without DCM (TPHFD), XC3S500E -4 | TPHFD | -0.77 |  |  | ns | LVCMOS25, IFD_DELAY_VALUE = default software setting (delay value 3) | 126 |+| Frequency of CCLK input, no bitstream compression, not using BUSY pin | FCCPAR | 0 |  | 50 | MHz | No bitstream compression; not using the BUSY pin | 149 |+| Frequency of CCLK input, no bitstream compression, using BUSY pin | FCCPAR | 0 |  | 66 | MHz | No bitstream compression; using the BUSY pin | 149 |+| Frequency of CCLK input, with bitstream compression | FCCPAR | 0 |  | 20 | MHz | With bitstream compression | 149 |+| High pulse width at CCLK input pin | TCCH | 5 |  |  | ns |  | 149 |+| Low pulse width at CCLK input pin | TCCL | 5 |  |  | ns |  | 149 |+| On-chip differential input termination |  |  | 120 |  | Ω | Across differential receiver terminals; available only in banks with VCCO = 2.5V | 17 |++## Materials and finish++As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).++| Part | Material | Colour / plating | Datasheet says | Page |+|---|---|---|---|---|+| contacts |  | tin | Dedicated pins(6) -0.5, VCCAUX + 0.5 V TIN Input signal transition time(7), - 500 ns | 117 |++## CAD (KiCad official)++- Symbol: `XC3S500E-4PQG208C`+- Footprint: `Package_QFP:PQFP-208_28x28mm_P0.5mm`+- 3D model: PQFP-208 (KiCad packages3D, STEP)+- 3D model files: `xc3s500e-4pqg208c-etched.step` / `xc3s500e-4pqg208c-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xc3s500e-4pqg208c.step` / `xc3s500e-4pqg208c.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [AMD XILINX datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590226762702888960) (227 pp, sha256 `9ef8122f74a48461`, retrieved 2026-10-21, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/xc3s500e-4pqg208c-datasheet.pdf)

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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "embedded processors & controllers",+    "xc3s500e-4pqg208c",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "xc3s500e-4pqg208c.kicad_sym",+    "xc3s500e-4pqg208c.kicad_mod",+    "xc3s500e-4pqg208c.glb",+    "xc3s500e-4pqg208c.step",+    "xc3s500e-4pqg208c.lbr",+    "docs/hero.png",+    "docs/xc3s500e-4pqg208c-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "xc3s500e-4pqg208c-hero.glb",+    "xc3s500e-4pqg208c-hero.overlay.json",+    "xc3s500e-4pqg208c-etched.glb"+  ],+  "component": {+    "mpn": "XC3S500E-4PQG208C",+    "manufacturer": "AMD XILINX",+    "package": "PQFP-208",+    "pin_count": 208,+    "category": "Embedded Processors & Controllers",+    "subcategory": "Programmable Logic Device (CPLDs/FPGAs)",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590226762702888960",+    "parts": {+      "symbol": "xc3s500e-4pqg208c.kicad_sym",+      "footprint": "xc3s500e-4pqg208c.kicad_mod",+      "model_3d": "xc3s500e-4pqg208c-hero.glb",+      "model_3d_plain": "xc3s500e-4pqg208c-etched.glb",+      "model_3d_step": "xc3s500e-4pqg208c-etched.step",+      "model_3d_step_plain": "xc3s500e-4pqg208c.step",+      "lbr": "xc3s500e-4pqg208c.lbr"+    },+    "distributor_links": {+      "lcsc": "C2976019",+      "digikey": "122-1520-ND",+      "mouser": "217-C3S500E-4PQG208C"+    },+    "distributor_check": {+      "checked_at": "2026-10-21T01:56:28Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "122-1520-ND",+        "status": "found",+        "lifecycle": "Obsolete"+      },+      "mouser": {+        "pn": "217-C3S500E-4PQG208C",+        "status": "found",+        "lifecycle": "End of Life"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "PROG_B",+        "type": "input",+        "description": "Active-Low program input; asserting it Low for 500 ns or longer restarts configuration, and an external 4.7 kΩ pull-up to 2.5V is recommended."+      },+      {+        "number": "2",+        "name": "IO_L01P_3",+        "type": "bidirectional",+        "description": "Differential pair L01 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "3",+        "name": "IO_L01N_3",+        "type": "bidirectional",+        "description": "Differential pair L01 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "4",+        "name": "IO_L02P_3",+        "type": "bidirectional",+        "description": "Differential pair L02 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "5",+        "name": "IO_L02N_3/VREF_3",+        "type": "bidirectional",+        "description": "Differential pair L02 inverted-line user I/O that serves as a VREF input for Bank 3; all VREF pins in the bank must be connected if used as a reference."+      },+      {+        "number": "6",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "7",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "8",+        "name": "IO_L03P_3",+        "type": "bidirectional",+        "description": "Differential pair L03 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "9",+        "name": "IO_L03N_3",+        "type": "bidirectional",+        "description": "Differential pair L03 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "11",+        "name": "IO_L04P_3",+        "type": "bidirectional",+        "description": "Differential pair L04 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "12",+        "name": "IO_L04N_3",+        "type": "bidirectional",+        "description": "Differential pair L04 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "13",+        "name": "VCCINT",+        "type": "power_in",+        "description": "Internal core logic supply pin that must be connected to +1.2V."+      },+      {+        "number": "14",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "15",+        "name": "IO_L05P_3",+        "type": "bidirectional",+        "description": "Differential pair L05 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "16",+        "name": "IO_L05N_3",+        "type": "bidirectional",+        "description": "Differential pair L05 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "17",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "18",+        "name": "IO_L06P_3",+        "type": "bidirectional",+        "description": "Differential pair L06 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "19",+        "name": "IO_L06N_3",+        "type": "bidirectional",+        "description": "Differential pair L06 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "20",+        "name": "IP/VREF_3",+        "type": "input",+        "description": "Input-only pin that is also a VREF input for Bank 3; all VREF pins in the bank must be connected if a reference voltage is used."+      },+      {+        "number": "21",+        "name": "VCCO_3",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "22",+        "name": "IO_L07P_3/LHCLK0",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK0 that is also a differential true-line user I/O in Bank 3."+      },+      {+        "number": "23",+        "name": "IO_L07N_3/LHCLK1",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK1 that is also a differential inverted-line user I/O in Bank 3."+      },+      {+        "number": "24",+        "name": "IO_L08P_3/LHCLK2",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK2 that is also a differential true-line user I/O in Bank 3."+      },+      {+        "number": "25",+        "name": "IO_L08N_3/LHCLK3",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK3 that is also a differential inverted-line user I/O in Bank 3."+      },+      {+        "number": "26",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "27",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "28",+        "name": "IO_L09P_3/LHCLK4",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK4 that is also a differential true-line user I/O in Bank 3."+      },+      {+        "number": "29",+        "name": "IO_L09N_3/LHCLK5",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK5 that is also a differential inverted-line user I/O in Bank 3."+      },+      {+        "number": "30",+        "name": "IO_L10P_3/LHCLK6",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK6 that is also a differential true-line user I/O in Bank 3."+      },+      {+        "number": "31",+        "name": "IO_L10N_3/LHCLK7",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK7 that is also a differential inverted-line user I/O in Bank 3."+      },+      {+        "number": "32",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "33",+        "name": "IO_L11P_3",+        "type": "bidirectional",+        "description": "Differential pair L11 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "34",+        "name": "IO_L11N_3",+        "type": "bidirectional",+        "description": "Differential pair L11 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "35",+        "name": "IO_L12P_3",+        "type": "bidirectional",+        "description": "Differential pair L12 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "36",+        "name": "IO_L12N_3",+        "type": "bidirectional",+        "description": "Differential pair L12 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "37",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "38",+        "name": "VCCO_3",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "39",+        "name": "IO_L13P_3",+        "type": "bidirectional",+        "description": "Differential pair L13 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "40",+        "name": "IO_L13N_3",+        "type": "bidirectional",+        "description": "Differential pair L13 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "41",+        "name": "IO_L14P_3",+        "type": "bidirectional",+        "description": "Differential pair L14 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "42",+        "name": "IO_L14N_3",+        "type": "bidirectional",+        "description": "Differential pair L14 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "43",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "44",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "45",+        "name": "IO/VREF_3",+        "type": "bidirectional",+        "description": "General-purpose user I/O that is also a VREF reference input for Bank 3; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "46",+        "name": "VCCO_3",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "47",+        "name": "IO_L15P_3",+        "type": "bidirectional",+        "description": "Differential pair L15 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "48",+        "name": "IO_L15N_3",+        "type": "bidirectional",+        "description": "Differential pair L15 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "49",+        "name": "IO_L16P_3",+        "type": "bidirectional",+        "description": "Differential pair L16 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "50",+        "name": "IO_L16N_3",+        "type": "bidirectional",+        "description": "Differential pair L16 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "51",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "52",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "53",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "54",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin in Bank 2 with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "55",+        "name": "IO_L01P_2/CSO_B",+        "type": "bidirectional",+        "description": "Dual-purpose CSO_B chip-select output (Active Low) during configuration, then a user I/O after configuration."+      },+      {+        "number": "56",+        "name": "IO_L01N_2/INIT_B",+        "type": "bidirectional",+        "description": "Open-drain INIT_B initialization indicator (Active Low) during configuration; drive High if unused as user I/O."+      },+      {+        "number": "57",+        "name": "IP_L02P_2",+        "type": "input",+        "description": "Input-only true-line pin of differential pair L02 in Bank 2; on-chip differential termination is not available on dedicated inputs."+      },+      {+        "number": "58",+        "name": "IP_L02N_2",+        "type": "input",+        "description": "Input-only inverted-line pin of differential pair L02 in Bank 2; on-chip differential termination is not available on dedicated inputs."+      },+      {+        "number": "59",+        "name": "VCCO_2",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 2, which must match the configuration source voltage and is an input to the Power-On Reset circuit."+      },+      {+        "number": "60",+        "name": "IO_L03P_2/DOUT/BUSY",+        "type": "bidirectional",+        "description": "Dual-purpose DOUT/BUSY pin that drives daisy-chain serial data or BUSY status during configuration, then is a user I/O."+      },+      {+        "number": "61",+        "name": "IO_L03N_2/MOSI/CSI_B",+        "type": "bidirectional",+        "description": "Dual-purpose MOSI (SPI) or CSI_B chip-select input (must be Low throughout parallel configuration), then a user I/O."+      },+      {+        "number": "62",+        "name": "IO_L04P_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 true line in Bank 2."+      },+      {+        "number": "63",+        "name": "IO_L04N_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 inverted line in Bank 2."+      },+      {+        "number": "64",+        "name": "IO_L05P_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L05 true line in Bank 2."+      },+      {+        "number": "65",+        "name": "IO_L05N_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L05 inverted line in Bank 2."+      },+      {+        "number": "66",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "67",+        "name": "VCCINT",+        "type": "power_in",+        "description": "Internal core logic supply pin that must be connected to +1.2V."+      },+      {+        "number": "68",+        "name": "IO_L06P_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L06 true line in Bank 2."+      },+      {+        "number": "69",+        "name": "IO_L06N_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L06 inverted line in Bank 2."+      },+      {+        "number": "70",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "71",+        "name": "IP_L07P_2",+        "type": "input",+        "description": "Input-only true-line pin of differential pair L07 in Bank 2."+      },+      {+        "number": "72",+        "name": "IP_L07N_2/VREF_2",+        "type": "input",+        "description": "Input-only inverted-line pin that is also a VREF input for Bank 2; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "73",+        "name": "VCCO_2",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 2; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "74",+        "name": "IO_L08P_2/D7/GCLK12",+        "type": "bidirectional",+        "description": "Dual-purpose D7 configuration data bit and global clock input GCLK12, usable as user I/O after configuration."+      },+      {+        "number": "75",+        "name": "IO_L08N_2/D6/GCLK13",+        "type": "bidirectional",+        "description": "Dual-purpose D6 configuration data bit and global clock input GCLK13, usable as user I/O after configuration."+      },+      {+        "number": "76",+        "name": "IO/D5",+        "type": "bidirectional",+        "description": "Dual-purpose D5 configuration data bit used in parallel modes, then a user I/O."+      },+      {+        "number": "77",+        "name": "IO_L09P_2/D4/GCLK14",+        "type": "bidirectional",+        "description": "Dual-purpose D4 configuration data bit and global clock input GCLK14, usable as user I/O after configuration."+      },+      {+        "number": "78",+        "name": "IO_L09N_2/D3/GCLK15",+        "type": "bidirectional",+        "description": "Dual-purpose D3 configuration data bit and global clock input GCLK15, usable as user I/O after configuration."+      },+      {+        "number": "79",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "80",+        "name": "IP_L10P_2/RDWR_B/GCLK0",+        "type": "bidirectional",+        "description": "Dual-purpose RDWR_B read/write control (must be Low during configuration) and global clock input GCLK0."+      },+      {+        "number": "81",+        "name": "IP_L10N_2/M2/GCLK1",+        "type": "bidirectional",+        "description": "Dual-purpose M2 mode-select pin sampled when INIT_B goes High, shared with global clock input GCLK1 (design note: avoid using GCLK1 as a clock)."+      },+      {+        "number": "82",+        "name": "IO_L11P_2/D2/GCLK2",+        "type": "bidirectional",+        "description": "Dual-purpose D2 configuration data bit and global clock input GCLK2, usable as user I/O after configuration."+      },+      {+        "number": "83",+        "name": "IO_L11N_2/D1/GCLK3",+        "type": "bidirectional",+        "description": "Dual-purpose D1 configuration data bit and global clock input GCLK3, usable as user I/O after configuration."+      },+      {+        "number": "84",+        "name": "IO/M1",+        "type": "input",+        "description": "Dual-purpose M1 mode-select pin that must be at a defined level when INIT_B goes High, then a user I/O."+      },+      {+        "number": "85",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "86",+        "name": "IO_L12P_2/M0",+        "type": "input",+        "description": "Dual-purpose M0 mode-select pin that must be at a defined level when INIT_B goes High, then a user I/O."+      },+      {+        "number": "87",+        "name": "IO_L12N_2/DIN/D0",+        "type": "input",+        "description": "Dual-purpose DIN/D0 serial configuration data input, then a user I/O after configuration."+      },+      {+        "number": "88",+        "name": "VCCO_2",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 2; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "89",+        "name": "IO_L13P_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 true line in Bank 2."+      },+      {+        "number": "90",+        "name": "IO_L13N_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 inverted line in Bank 2."+      },+      {+        "number": "91",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "92",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "93",+        "name": "IO_L14P_2/A23",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A23 used in parallel Flash configuration, then a user I/O."+      },+      {+        "number": "94",+        "name": "IO_L14N_2/A22",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A22 used in parallel Flash configuration, then a user I/O."+      },+      {+        "number": "95",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "96",+        "name": "IO_L15P_2/A21",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A21 used in parallel Flash configuration, then a user I/O."+      },+      {+        "number": "97",+        "name": "IO_L15N_2/A20",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A20 used in parallel Flash configuration, then a user I/O."+      },+      {+        "number": "98",+        "name": "IO/VREF_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O that is also a VREF input for Bank 2; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "99",+        "name": "IO_L16P_2/VS2/A19",+        "type": "bidirectional",+        "description": "Dual-purpose SPI variant-select VS2 (sampled when INIT_B goes High) and BPI address line A19, then a user I/O."+      },+      {+        "number": "100",+        "name": "IO_L16N_2/VS1/A18",+        "type": "bidirectional",+        "description": "Dual-purpose SPI variant-select VS1 (sampled when INIT_B goes High) and BPI address line A18, then a user I/O."+      },+      {+        "number": "101",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "102",+        "name": "IO_L17P_2/VS0/A17",+        "type": "bidirectional",+        "description": "Dual-purpose SPI variant-select VS0 (sampled when INIT_B goes High) and BPI address line A17, then a user I/O."+      },+      {+        "number": "103",+        "name": "IO_L17N_2/CCLK",+        "type": "bidirectional",+        "description": "Dual-purpose configuration clock CCLK, driven by the FPGA in master modes and an input in slave modes, then a user I/O."+      },+      {+        "number": "104",+        "name": "DONE",+        "type": "bidirectional",+        "description": "Open-drain configuration DONE indicator that goes High when configuration completes and requires an external 330 Ω pull-up to 2.5V."+      },+      {+        "number": "105",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "106",+        "name": "IO_L01P_1/A16",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A16 used in parallel Flash configuration, then a user I/O (differential pair L01 true line)."+      },+      {+        "number": "107",+        "name": "IO_L01N_1/A15",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A15 used in parallel Flash configuration, then a user I/O (differential pair L01 inverted line)."+      },+      {+        "number": "108",+        "name": "IO_L02P_1/A14",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A14 used in parallel Flash configuration, then a user I/O (differential pair L02 true line)."+      },+      {+        "number": "109",+        "name": "IO_L02N_1/A13",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A13 used in parallel Flash configuration, then a user I/O (differential pair L02 inverted line)."+      },+      {+        "number": "110",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "111",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "112",+        "name": "IO_L03P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L03 true line in Bank 1."+      },+      {+        "number": "113",+        "name": "IO_L03N_1/VREF_1",+        "type": "bidirectional",+        "description": "Differential pair L03 inverted-line user I/O that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "114",+        "name": "VCCO_1",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "115",+        "name": "IO_L04P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 true line in Bank 1."+      },+      {+        "number": "116",+        "name": "IO_L04N_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 inverted line in Bank 1."+      },+      {+        "number": "117",+        "name": "VCCINT",+        "type": "power_in",+        "description": "Internal core logic supply pin that must be connected to +1.2V."+      },+      {+        "number": "118",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "119",+        "name": "IO_L05P_1/A12",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A12 used in parallel Flash configuration, then a user I/O (differential pair L05 true line)."+      },+      {+        "number": "120",+        "name": "IO_L05N_1/A11",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A11 used in parallel Flash configuration, then a user I/O (differential pair L05 inverted line)."+      },+      {+        "number": "121",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "122",+        "name": "IO_L06P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L06 true line in Bank 1."+      },+      {+        "number": "123",+        "name": "IO_L06N_1/VREF_1",+        "type": "bidirectional",+        "description": "Differential pair L06 inverted-line user I/O that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "124",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "125",+        "name": "VCCO_1",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "126",+        "name": "IO_L07P_1/A10/RHCLK0",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK0 and dual-purpose BPI address line A10, then a user I/O."+      },+      {+        "number": "127",+        "name": "IO_L07N_1/A9/RHCLK1",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK1 and dual-purpose BPI address line A9, then a user I/O."+      },+      {+        "number": "128",+        "name": "IO_L08P_1/A8/RHCLK2",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK2 and dual-purpose BPI address line A8, then a user I/O."+      },+      {+        "number": "129",+        "name": "IO_L08N_1/A7/RHCLK3",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK3 and dual-purpose BPI address line A7, then a user I/O."+      },+      {+        "number": "130",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "131",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "132",+        "name": "IO_L09P_1/A6/RHCLK4",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK4 and dual-purpose BPI address line A6, then a user I/O."+      },+      {+        "number": "133",+        "name": "IO_L09N_1/A5/RHCLK5",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK5 and dual-purpose BPI address line A5, then a user I/O."+      },+      {+        "number": "134",+        "name": "IO_L10P_1/A4/RHCLK6",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK6 and dual-purpose BPI address line A4, then a user I/O."+      },+      {+        "number": "135",+        "name": "IO_L10N_1/A3/RHCLK7",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK7 and dual-purpose BPI address line A3, then a user I/O."+      },+      {+        "number": "136",+        "name": "IP/VREF_1",+        "type": "input",+        "description": "Input-only pin that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "137",+        "name": "IO_L11P_1/A2",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A2 used in parallel Flash configuration, then a user I/O (differential pair L11 true line)."+      },+      {+        "number": "138",+        "name": "IO_L11N_1/A1",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A1 used in parallel Flash configuration, then a user I/O (differential pair L11 inverted line)."+      },+      {+        "number": "139",+        "name": "IO_L12P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L12 true line in Bank 1."+      },+      {+        "number": "140",+        "name": "IO_L12N_1/A0",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A0 used in parallel Flash configuration, then a user I/O (differential pair L12 inverted line)."+      },+      {+        "number": "141",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "142",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "143",+        "name": "VCCO_1",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "144",+        "name": "IO_L13P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 true line in Bank 1."+      },+      {+        "number": "145",+        "name": "IO_L13N_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 inverted line in Bank 1."+      },+      {+        "number": "146",+        "name": "IO_L14P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L14 true line in Bank 1."+      },+      {+        "number": "147",+        "name": "IO_L14N_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L14 inverted line in Bank 1."+      },+      {+        "number": "148",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "149",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "150",+        "name": "IO_L15P_1/HDC",+        "type": "bidirectional",+        "description": "Dual-purpose HDC parallel Flash write-enable (WE#) output during configuration, then a user I/O."+      },+      {+        "number": "151",+        "name": "IO_L15N_1/LDC0",+        "type": "bidirectional",+        "description": "Dual-purpose LDC0 parallel Flash chip-enable (CE#) output driven Low during configuration, then a user I/O."+      },+      {+        "number": "152",+        "name": "IO_L16P_1/LDC1",+        "type": "bidirectional",+        "description": "Dual-purpose LDC1 parallel Flash output-enable (OE#) driven Low during configuration, then a user I/O."+      },+      {+        "number": "153",+        "name": "IO_L16N_1/LDC2",+        "type": "bidirectional",+        "description": "Dual-purpose LDC2 parallel Flash BYTE# control, driven Low during configuration, then a user I/O."+      },+      {+        "number": "154",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "155",+        "name": "TMS",+        "type": "input",+        "description": "Dedicated JTAG test mode select input, powered by VCCAUX."+      },+      {+        "number": "156",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "157",+        "name": "TDO",+        "type": "output",+        "description": "Dedicated JTAG test data output, powered by VCCAUX."+      },+      {+        "number": "158",+        "name": "TCK",+        "type": "input",+        "description": "Dedicated JTAG test clock input, powered by VCCAUX."+      },+      {+        "number": "159",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "160",+        "name": "IO_L01P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L01 true line in Bank 0."+      },+      {+        "number": "161",+        "name": "IO_L01N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L01 inverted line in Bank 0."+      },+      {+        "number": "162",+        "name": "IO_L02P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L02 true line in Bank 0."+      },+      {+        "number": "163",+        "name": "IO_L02N_0/VREF_0",+        "type": "bidirectional",+        "description": "Differential pair L02 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "164",+        "name": "IO_L03P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L03 true line in Bank 0."+      },+      {+        "number": "165",+        "name": "IO_L03N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L03 inverted line in Bank 0."+      },+      {+        "number": "166",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "167",+        "name": "IO_L04P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 true line in Bank 0."+      },+      {+        "number": "168",+        "name": "IO_L04N_0/VREF_0",+        "type": "bidirectional",+        "description": "Differential pair L04 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "169",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "170",+        "name": "VCCINT",+        "type": "power_in",+        "description": "Internal core logic supply pin that must be connected to +1.2V."+      },+      {+        "number": "171",+        "name": "IO_L05P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L05 true line in Bank 0."+      },+      {+        "number": "172",+        "name": "IO_L05N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L05 inverted line in Bank 0."+      },+      {+        "number": "173",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "174",+        "name": "IP_L06P_0",+        "type": "input",+        "description": "Input-only true-line pin of differential pair L06 in Bank 0 with no output structure or differential termination."+      },+      {+        "number": "175",+        "name": "IP_L06N_0",+        "type": "input",+        "description": "Input-only inverted-line pin of differential pair L06 in Bank 0 with no output structure or differential termination."+      },+      {+        "number": "176",+        "name": "VCCO_0",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "177",+        "name": "IO_L07P_0/GCLK4",+        "type": "bidirectional",+        "description": "Global clock input GCLK4 that is also a differential true-line user I/O in Bank 0."+      },+      {+        "number": "178",+        "name": "IO_L07N_0/GCLK5",+        "type": "bidirectional",+        "description": "Global clock input GCLK5 that is also a differential inverted-line user I/O in Bank 0."+      },+      {+        "number": "179",+        "name": "IO/VREF_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "180",+        "name": "IO_L08P_0/GCLK6",+        "type": "bidirectional",+        "description": "Global clock input GCLK6 that is also a differential true-line user I/O in Bank 0."+      },+      {+        "number": "181",+        "name": "IO_L08N_0/GCLK7",+        "type": "bidirectional",+        "description": "Global clock input GCLK7 that is also a differential inverted-line user I/O in Bank 0."+      },+      {+        "number": "182",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "183",+        "name": "IP_L09P_0/GCLK8",+        "type": "bidirectional",+        "description": "Global clock input GCLK8 that is also a differential true-line pin in Bank 0."+      },+      {+        "number": "184",+        "name": "IP_L09N_0/GCLK9",+        "type": "bidirectional",+        "description": "Global clock input GCLK9 that is also a differential inverted-line pin in Bank 0."+      },+      {+        "number": "185",+        "name": "IO_L10P_0/GCLK10",+        "type": "bidirectional",+        "description": "Global clock input GCLK10 that is also a differential true-line user I/O in Bank 0."+      },+      {+        "number": "186",+        "name": "IO_L10N_0/GCLK11",+        "type": "bidirectional",+        "description": "Global clock input GCLK11 that is also a differential inverted-line user I/O in Bank 0."+      },+      {+        "number": "187",+        "name": "IO",+        "type": "bidirectional",+        "description": "Unrestricted general-purpose user I/O in Bank 0."+      },+      {+        "number": "188",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "189",+        "name": "IO_L11P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L11 true line in Bank 0."+      },+      {+        "number": "190",+        "name": "IO_L11N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L11 inverted line in Bank 0."+      },+      {+        "number": "191",+        "name": "VCCO_0",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "192",+        "name": "IO_L12P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L12 true line in Bank 0."+      },+      {+        "number": "193",+        "name": "IO_L12N_0/VREF_0",+        "type": "bidirectional",+        "description": "Differential pair L12 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "194",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "195",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "196",+        "name": "IO_L13P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 true line in Bank 0."+      },+      {+        "number": "197",+        "name": "IO_L13N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 inverted line in Bank 0."+      },+      {+        "number": "198",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "199",+        "name": "IO_L14P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L14 true line in Bank 0."+      },+      {+        "number": "200",+        "name": "IO_L14N_0/VREF_0",+        "type": "bidirectional",+        "description": "Differential pair L14 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "201",+        "name": "VCCO_0",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "202",+        "name": "IO_L15P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L15 true line in Bank 0."+      },+      {+        "number": "203",+        "name": "IO_L15N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L15 inverted line in Bank 0."+      },+      {+        "number": "204",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "205",+        "name": "IO_L16P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L16 true line in Bank 0."+      },+      {+        "number": "206",+        "name": "IO_L16N_0/HSWAP",+        "type": "bidirectional",+        "description": "Dual-purpose HSWAP pin: Low enables pull-up resistors on all user I/O during configuration, High disables them; then a user I/O."+      },+      {+        "number": "207",+        "name": "TDI",+        "type": "input",+        "description": "Dedicated JTAG test data input, powered by VCCAUX."+      },+      {+        "number": "208",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The datasheet tabulates the PQ208 pinout (Table 140, labeled PQ208 / PQG208 package family). The ord; Table 140 lists pin names for the XC3S250E and XC3S500E together (identical footprint); the names ab; Per-pin descriptions are not individually written in the datasheet. They were composed from the pin-",+          "79/208 pins cited to the wrong page (name found elsewhere): ['55:IO_L01P_2/CSO_B@p181', '60:IO_L03P_2/DOUT/BUSY@p181', '61:IO_L03N_2/MOSI/CSI_B@p181', '62:IO_L04P_2@p181']"+        ],+        "pages_sent": 94,+        "cost_usd": 0.8727,+        "at": "2026-10-21T01:50:50"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590226762702888960",+        "pages": 227,+        "sha256": "9ef8122f74a48461",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 208,+        "described": 208,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "xc3s500e-4pqg208c.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          30.93,+          30.93,+          1.6+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "6b5c689015c2fe4ec3afe0ef6e3f9325182a25b05257e4722c7b62133a27ecc8",+        "checked": "2026-10-21",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "xc3s500e-4pqg208c-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          30.93,+          30.93,+          1.6+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "6c501ded5c661dd98769e742bdbfc9352f6db5dd0381b59fe0ddbc2190e41faa",+        "checked": "2026-10-21",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  }+}

@@ -0,0 +1,1403 @@+{+  "slug": "xc3s500e-4pqg208c",+  "version": "0.1.0",+  "type": "component",+  "description": "AMD XILINX Programmable Logic Device (CPLDs/FPGAs), PQFP-208. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "embedded processors & controllers",+    "xc3s500e-4pqg208c",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "xc3s500e-4pqg208c.kicad_sym",+    "xc3s500e-4pqg208c.kicad_mod",+    "xc3s500e-4pqg208c.glb",+    "xc3s500e-4pqg208c.step",+    "xc3s500e-4pqg208c.lbr",+    "docs/hero.png",+    "docs/xc3s500e-4pqg208c-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "xc3s500e-4pqg208c-hero.glb",+    "xc3s500e-4pqg208c-hero.overlay.json",+    "xc3s500e-4pqg208c-etched.glb"+  ],+  "component": {+    "mpn": "XC3S500E-4PQG208C",+    "manufacturer": "AMD XILINX",+    "package": "PQFP-208",+    "pin_count": 208,+    "category": "Embedded Processors & Controllers",+    "subcategory": "Programmable Logic Device (CPLDs/FPGAs)",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590226762702888960",+    "parts": {+      "symbol": "xc3s500e-4pqg208c.kicad_sym",+      "footprint": "xc3s500e-4pqg208c.kicad_mod",+      "model_3d": "xc3s500e-4pqg208c-hero.glb",+      "model_3d_plain": "xc3s500e-4pqg208c-etched.glb",+      "model_3d_step": "xc3s500e-4pqg208c-etched.step",+      "model_3d_step_plain": "xc3s500e-4pqg208c.step",+      "lbr": "xc3s500e-4pqg208c.lbr"+    },+    "distributor_links": {+      "lcsc": "C2976019",+      "digikey": "122-1520-ND",+      "mouser": "217-C3S500E-4PQG208C"+    },+    "distributor_check": {+      "checked_at": "2026-10-21T01:56:28Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "122-1520-ND",+        "status": "found",+        "lifecycle": "Obsolete"+      },+      "mouser": {+        "pn": "217-C3S500E-4PQG208C",+        "status": "found",+        "lifecycle": "End of Life"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "PROG_B",+        "type": "input",+        "description": "Active-Low program input; asserting it Low for 500 ns or longer restarts configuration, and an external 4.7 kΩ pull-up to 2.5V is recommended."+      },+      {+        "number": "2",+        "name": "IO_L01P_3",+        "type": "bidirectional",+        "description": "Differential pair L01 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "3",+        "name": "IO_L01N_3",+        "type": "bidirectional",+        "description": "Differential pair L01 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "4",+        "name": "IO_L02P_3",+        "type": "bidirectional",+        "description": "Differential pair L02 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "5",+        "name": "IO_L02N_3/VREF_3",+        "type": "bidirectional",+        "description": "Differential pair L02 inverted-line user I/O that serves as a VREF input for Bank 3; all VREF pins in the bank must be connected if used as a reference."+      },+      {+        "number": "6",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "7",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "8",+        "name": "IO_L03P_3",+        "type": "bidirectional",+        "description": "Differential pair L03 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "9",+        "name": "IO_L03N_3",+        "type": "bidirectional",+        "description": "Differential pair L03 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "11",+        "name": "IO_L04P_3",+        "type": "bidirectional",+        "description": "Differential pair L04 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "12",+        "name": "IO_L04N_3",+        "type": "bidirectional",+        "description": "Differential pair L04 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "13",+        "name": "VCCINT",+        "type": "power_in",+        "description": "Internal core logic supply pin that must be connected to +1.2V."+      },+      {+        "number": "14",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "15",+        "name": "IO_L05P_3",+        "type": "bidirectional",+        "description": "Differential pair L05 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "16",+        "name": "IO_L05N_3",+        "type": "bidirectional",+        "description": "Differential pair L05 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "17",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "18",+        "name": "IO_L06P_3",+        "type": "bidirectional",+        "description": "Differential pair L06 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "19",+        "name": "IO_L06N_3",+        "type": "bidirectional",+        "description": "Differential pair L06 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "20",+        "name": "IP/VREF_3",+        "type": "input",+        "description": "Input-only pin that is also a VREF input for Bank 3; all VREF pins in the bank must be connected if a reference voltage is used."+      },+      {+        "number": "21",+        "name": "VCCO_3",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "22",+        "name": "IO_L07P_3/LHCLK0",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK0 that is also a differential true-line user I/O in Bank 3."+      },+      {+        "number": "23",+        "name": "IO_L07N_3/LHCLK1",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK1 that is also a differential inverted-line user I/O in Bank 3."+      },+      {+        "number": "24",+        "name": "IO_L08P_3/LHCLK2",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK2 that is also a differential true-line user I/O in Bank 3."+      },+      {+        "number": "25",+        "name": "IO_L08N_3/LHCLK3",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK3 that is also a differential inverted-line user I/O in Bank 3."+      },+      {+        "number": "26",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "27",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "28",+        "name": "IO_L09P_3/LHCLK4",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK4 that is also a differential true-line user I/O in Bank 3."+      },+      {+        "number": "29",+        "name": "IO_L09N_3/LHCLK5",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK5 that is also a differential inverted-line user I/O in Bank 3."+      },+      {+        "number": "30",+        "name": "IO_L10P_3/LHCLK6",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK6 that is also a differential true-line user I/O in Bank 3."+      },+      {+        "number": "31",+        "name": "IO_L10N_3/LHCLK7",+        "type": "bidirectional",+        "description": "Left-half clock input LHCLK7 that is also a differential inverted-line user I/O in Bank 3."+      },+      {+        "number": "32",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "33",+        "name": "IO_L11P_3",+        "type": "bidirectional",+        "description": "Differential pair L11 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "34",+        "name": "IO_L11N_3",+        "type": "bidirectional",+        "description": "Differential pair L11 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "35",+        "name": "IO_L12P_3",+        "type": "bidirectional",+        "description": "Differential pair L12 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "36",+        "name": "IO_L12N_3",+        "type": "bidirectional",+        "description": "Differential pair L12 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "37",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "38",+        "name": "VCCO_3",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "39",+        "name": "IO_L13P_3",+        "type": "bidirectional",+        "description": "Differential pair L13 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "40",+        "name": "IO_L13N_3",+        "type": "bidirectional",+        "description": "Differential pair L13 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "41",+        "name": "IO_L14P_3",+        "type": "bidirectional",+        "description": "Differential pair L14 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "42",+        "name": "IO_L14N_3",+        "type": "bidirectional",+        "description": "Differential pair L14 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "43",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "44",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "45",+        "name": "IO/VREF_3",+        "type": "bidirectional",+        "description": "General-purpose user I/O that is also a VREF reference input for Bank 3; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "46",+        "name": "VCCO_3",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "47",+        "name": "IO_L15P_3",+        "type": "bidirectional",+        "description": "Differential pair L15 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "48",+        "name": "IO_L15N_3",+        "type": "bidirectional",+        "description": "Differential pair L15 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "49",+        "name": "IO_L16P_3",+        "type": "bidirectional",+        "description": "Differential pair L16 true-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "50",+        "name": "IO_L16N_3",+        "type": "bidirectional",+        "description": "Differential pair L16 inverted-line general-purpose user I/O in Bank 3."+      },+      {+        "number": "51",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "52",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "53",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "54",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin in Bank 2 with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "55",+        "name": "IO_L01P_2/CSO_B",+        "type": "bidirectional",+        "description": "Dual-purpose CSO_B chip-select output (Active Low) during configuration, then a user I/O after configuration."+      },+      {+        "number": "56",+        "name": "IO_L01N_2/INIT_B",+        "type": "bidirectional",+        "description": "Open-drain INIT_B initialization indicator (Active Low) during configuration; drive High if unused as user I/O."+      },+      {+        "number": "57",+        "name": "IP_L02P_2",+        "type": "input",+        "description": "Input-only true-line pin of differential pair L02 in Bank 2; on-chip differential termination is not available on dedicated inputs."+      },+      {+        "number": "58",+        "name": "IP_L02N_2",+        "type": "input",+        "description": "Input-only inverted-line pin of differential pair L02 in Bank 2; on-chip differential termination is not available on dedicated inputs."+      },+      {+        "number": "59",+        "name": "VCCO_2",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 2, which must match the configuration source voltage and is an input to the Power-On Reset circuit."+      },+      {+        "number": "60",+        "name": "IO_L03P_2/DOUT/BUSY",+        "type": "bidirectional",+        "description": "Dual-purpose DOUT/BUSY pin that drives daisy-chain serial data or BUSY status during configuration, then is a user I/O."+      },+      {+        "number": "61",+        "name": "IO_L03N_2/MOSI/CSI_B",+        "type": "bidirectional",+        "description": "Dual-purpose MOSI (SPI) or CSI_B chip-select input (must be Low throughout parallel configuration), then a user I/O."+      },+      {+        "number": "62",+        "name": "IO_L04P_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 true line in Bank 2."+      },+      {+        "number": "63",+        "name": "IO_L04N_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 inverted line in Bank 2."+      },+      {+        "number": "64",+        "name": "IO_L05P_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L05 true line in Bank 2."+      },+      {+        "number": "65",+        "name": "IO_L05N_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L05 inverted line in Bank 2."+      },+      {+        "number": "66",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "67",+        "name": "VCCINT",+        "type": "power_in",+        "description": "Internal core logic supply pin that must be connected to +1.2V."+      },+      {+        "number": "68",+        "name": "IO_L06P_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L06 true line in Bank 2."+      },+      {+        "number": "69",+        "name": "IO_L06N_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L06 inverted line in Bank 2."+      },+      {+        "number": "70",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "71",+        "name": "IP_L07P_2",+        "type": "input",+        "description": "Input-only true-line pin of differential pair L07 in Bank 2."+      },+      {+        "number": "72",+        "name": "IP_L07N_2/VREF_2",+        "type": "input",+        "description": "Input-only inverted-line pin that is also a VREF input for Bank 2; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "73",+        "name": "VCCO_2",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 2; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "74",+        "name": "IO_L08P_2/D7/GCLK12",+        "type": "bidirectional",+        "description": "Dual-purpose D7 configuration data bit and global clock input GCLK12, usable as user I/O after configuration."+      },+      {+        "number": "75",+        "name": "IO_L08N_2/D6/GCLK13",+        "type": "bidirectional",+        "description": "Dual-purpose D6 configuration data bit and global clock input GCLK13, usable as user I/O after configuration."+      },+      {+        "number": "76",+        "name": "IO/D5",+        "type": "bidirectional",+        "description": "Dual-purpose D5 configuration data bit used in parallel modes, then a user I/O."+      },+      {+        "number": "77",+        "name": "IO_L09P_2/D4/GCLK14",+        "type": "bidirectional",+        "description": "Dual-purpose D4 configuration data bit and global clock input GCLK14, usable as user I/O after configuration."+      },+      {+        "number": "78",+        "name": "IO_L09N_2/D3/GCLK15",+        "type": "bidirectional",+        "description": "Dual-purpose D3 configuration data bit and global clock input GCLK15, usable as user I/O after configuration."+      },+      {+        "number": "79",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "80",+        "name": "IP_L10P_2/RDWR_B/GCLK0",+        "type": "bidirectional",+        "description": "Dual-purpose RDWR_B read/write control (must be Low during configuration) and global clock input GCLK0."+      },+      {+        "number": "81",+        "name": "IP_L10N_2/M2/GCLK1",+        "type": "bidirectional",+        "description": "Dual-purpose M2 mode-select pin sampled when INIT_B goes High, shared with global clock input GCLK1 (design note: avoid using GCLK1 as a clock)."+      },+      {+        "number": "82",+        "name": "IO_L11P_2/D2/GCLK2",+        "type": "bidirectional",+        "description": "Dual-purpose D2 configuration data bit and global clock input GCLK2, usable as user I/O after configuration."+      },+      {+        "number": "83",+        "name": "IO_L11N_2/D1/GCLK3",+        "type": "bidirectional",+        "description": "Dual-purpose D1 configuration data bit and global clock input GCLK3, usable as user I/O after configuration."+      },+      {+        "number": "84",+        "name": "IO/M1",+        "type": "input",+        "description": "Dual-purpose M1 mode-select pin that must be at a defined level when INIT_B goes High, then a user I/O."+      },+      {+        "number": "85",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "86",+        "name": "IO_L12P_2/M0",+        "type": "input",+        "description": "Dual-purpose M0 mode-select pin that must be at a defined level when INIT_B goes High, then a user I/O."+      },+      {+        "number": "87",+        "name": "IO_L12N_2/DIN/D0",+        "type": "input",+        "description": "Dual-purpose DIN/D0 serial configuration data input, then a user I/O after configuration."+      },+      {+        "number": "88",+        "name": "VCCO_2",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 2; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "89",+        "name": "IO_L13P_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 true line in Bank 2."+      },+      {+        "number": "90",+        "name": "IO_L13N_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 inverted line in Bank 2."+      },+      {+        "number": "91",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "92",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "93",+        "name": "IO_L14P_2/A23",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A23 used in parallel Flash configuration, then a user I/O."+      },+      {+        "number": "94",+        "name": "IO_L14N_2/A22",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A22 used in parallel Flash configuration, then a user I/O."+      },+      {+        "number": "95",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "96",+        "name": "IO_L15P_2/A21",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A21 used in parallel Flash configuration, then a user I/O."+      },+      {+        "number": "97",+        "name": "IO_L15N_2/A20",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A20 used in parallel Flash configuration, then a user I/O."+      },+      {+        "number": "98",+        "name": "IO/VREF_2",+        "type": "bidirectional",+        "description": "General-purpose user I/O that is also a VREF input for Bank 2; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "99",+        "name": "IO_L16P_2/VS2/A19",+        "type": "bidirectional",+        "description": "Dual-purpose SPI variant-select VS2 (sampled when INIT_B goes High) and BPI address line A19, then a user I/O."+      },+      {+        "number": "100",+        "name": "IO_L16N_2/VS1/A18",+        "type": "bidirectional",+        "description": "Dual-purpose SPI variant-select VS1 (sampled when INIT_B goes High) and BPI address line A18, then a user I/O."+      },+      {+        "number": "101",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "102",+        "name": "IO_L17P_2/VS0/A17",+        "type": "bidirectional",+        "description": "Dual-purpose SPI variant-select VS0 (sampled when INIT_B goes High) and BPI address line A17, then a user I/O."+      },+      {+        "number": "103",+        "name": "IO_L17N_2/CCLK",+        "type": "bidirectional",+        "description": "Dual-purpose configuration clock CCLK, driven by the FPGA in master modes and an input in slave modes, then a user I/O."+      },+      {+        "number": "104",+        "name": "DONE",+        "type": "bidirectional",+        "description": "Open-drain configuration DONE indicator that goes High when configuration completes and requires an external 330 Ω pull-up to 2.5V."+      },+      {+        "number": "105",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "106",+        "name": "IO_L01P_1/A16",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A16 used in parallel Flash configuration, then a user I/O (differential pair L01 true line)."+      },+      {+        "number": "107",+        "name": "IO_L01N_1/A15",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A15 used in parallel Flash configuration, then a user I/O (differential pair L01 inverted line)."+      },+      {+        "number": "108",+        "name": "IO_L02P_1/A14",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A14 used in parallel Flash configuration, then a user I/O (differential pair L02 true line)."+      },+      {+        "number": "109",+        "name": "IO_L02N_1/A13",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A13 used in parallel Flash configuration, then a user I/O (differential pair L02 inverted line)."+      },+      {+        "number": "110",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "111",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "112",+        "name": "IO_L03P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L03 true line in Bank 1."+      },+      {+        "number": "113",+        "name": "IO_L03N_1/VREF_1",+        "type": "bidirectional",+        "description": "Differential pair L03 inverted-line user I/O that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "114",+        "name": "VCCO_1",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "115",+        "name": "IO_L04P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 true line in Bank 1."+      },+      {+        "number": "116",+        "name": "IO_L04N_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 inverted line in Bank 1."+      },+      {+        "number": "117",+        "name": "VCCINT",+        "type": "power_in",+        "description": "Internal core logic supply pin that must be connected to +1.2V."+      },+      {+        "number": "118",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "119",+        "name": "IO_L05P_1/A12",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A12 used in parallel Flash configuration, then a user I/O (differential pair L05 true line)."+      },+      {+        "number": "120",+        "name": "IO_L05N_1/A11",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A11 used in parallel Flash configuration, then a user I/O (differential pair L05 inverted line)."+      },+      {+        "number": "121",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "122",+        "name": "IO_L06P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L06 true line in Bank 1."+      },+      {+        "number": "123",+        "name": "IO_L06N_1/VREF_1",+        "type": "bidirectional",+        "description": "Differential pair L06 inverted-line user I/O that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "124",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "125",+        "name": "VCCO_1",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "126",+        "name": "IO_L07P_1/A10/RHCLK0",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK0 and dual-purpose BPI address line A10, then a user I/O."+      },+      {+        "number": "127",+        "name": "IO_L07N_1/A9/RHCLK1",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK1 and dual-purpose BPI address line A9, then a user I/O."+      },+      {+        "number": "128",+        "name": "IO_L08P_1/A8/RHCLK2",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK2 and dual-purpose BPI address line A8, then a user I/O."+      },+      {+        "number": "129",+        "name": "IO_L08N_1/A7/RHCLK3",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK3 and dual-purpose BPI address line A7, then a user I/O."+      },+      {+        "number": "130",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "131",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "132",+        "name": "IO_L09P_1/A6/RHCLK4",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK4 and dual-purpose BPI address line A6, then a user I/O."+      },+      {+        "number": "133",+        "name": "IO_L09N_1/A5/RHCLK5",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK5 and dual-purpose BPI address line A5, then a user I/O."+      },+      {+        "number": "134",+        "name": "IO_L10P_1/A4/RHCLK6",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK6 and dual-purpose BPI address line A4, then a user I/O."+      },+      {+        "number": "135",+        "name": "IO_L10N_1/A3/RHCLK7",+        "type": "bidirectional",+        "description": "Right-half clock input RHCLK7 and dual-purpose BPI address line A3, then a user I/O."+      },+      {+        "number": "136",+        "name": "IP/VREF_1",+        "type": "input",+        "description": "Input-only pin that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "137",+        "name": "IO_L11P_1/A2",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A2 used in parallel Flash configuration, then a user I/O (differential pair L11 true line)."+      },+      {+        "number": "138",+        "name": "IO_L11N_1/A1",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A1 used in parallel Flash configuration, then a user I/O (differential pair L11 inverted line)."+      },+      {+        "number": "139",+        "name": "IO_L12P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L12 true line in Bank 1."+      },+      {+        "number": "140",+        "name": "IO_L12N_1/A0",+        "type": "bidirectional",+        "description": "Dual-purpose BPI address line A0 used in parallel Flash configuration, then a user I/O (differential pair L12 inverted line)."+      },+      {+        "number": "141",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "142",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "143",+        "name": "VCCO_1",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "144",+        "name": "IO_L13P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 true line in Bank 1."+      },+      {+        "number": "145",+        "name": "IO_L13N_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 inverted line in Bank 1."+      },+      {+        "number": "146",+        "name": "IO_L14P_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L14 true line in Bank 1."+      },+      {+        "number": "147",+        "name": "IO_L14N_1",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L14 inverted line in Bank 1."+      },+      {+        "number": "148",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "149",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "150",+        "name": "IO_L15P_1/HDC",+        "type": "bidirectional",+        "description": "Dual-purpose HDC parallel Flash write-enable (WE#) output during configuration, then a user I/O."+      },+      {+        "number": "151",+        "name": "IO_L15N_1/LDC0",+        "type": "bidirectional",+        "description": "Dual-purpose LDC0 parallel Flash chip-enable (CE#) output driven Low during configuration, then a user I/O."+      },+      {+        "number": "152",+        "name": "IO_L16P_1/LDC1",+        "type": "bidirectional",+        "description": "Dual-purpose LDC1 parallel Flash output-enable (OE#) driven Low during configuration, then a user I/O."+      },+      {+        "number": "153",+        "name": "IO_L16N_1/LDC2",+        "type": "bidirectional",+        "description": "Dual-purpose LDC2 parallel Flash BYTE# control, driven Low during configuration, then a user I/O."+      },+      {+        "number": "154",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "155",+        "name": "TMS",+        "type": "input",+        "description": "Dedicated JTAG test mode select input, powered by VCCAUX."+      },+      {+        "number": "156",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "157",+        "name": "TDO",+        "type": "output",+        "description": "Dedicated JTAG test data output, powered by VCCAUX."+      },+      {+        "number": "158",+        "name": "TCK",+        "type": "input",+        "description": "Dedicated JTAG test clock input, powered by VCCAUX."+      },+      {+        "number": "159",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "160",+        "name": "IO_L01P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L01 true line in Bank 0."+      },+      {+        "number": "161",+        "name": "IO_L01N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L01 inverted line in Bank 0."+      },+      {+        "number": "162",+        "name": "IO_L02P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L02 true line in Bank 0."+      },+      {+        "number": "163",+        "name": "IO_L02N_0/VREF_0",+        "type": "bidirectional",+        "description": "Differential pair L02 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "164",+        "name": "IO_L03P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L03 true line in Bank 0."+      },+      {+        "number": "165",+        "name": "IO_L03N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L03 inverted line in Bank 0."+      },+      {+        "number": "166",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "167",+        "name": "IO_L04P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L04 true line in Bank 0."+      },+      {+        "number": "168",+        "name": "IO_L04N_0/VREF_0",+        "type": "bidirectional",+        "description": "Differential pair L04 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "169",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "170",+        "name": "VCCINT",+        "type": "power_in",+        "description": "Internal core logic supply pin that must be connected to +1.2V."+      },+      {+        "number": "171",+        "name": "IO_L05P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L05 true line in Bank 0."+      },+      {+        "number": "172",+        "name": "IO_L05N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L05 inverted line in Bank 0."+      },+      {+        "number": "173",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "174",+        "name": "IP_L06P_0",+        "type": "input",+        "description": "Input-only true-line pin of differential pair L06 in Bank 0 with no output structure or differential termination."+      },+      {+        "number": "175",+        "name": "IP_L06N_0",+        "type": "input",+        "description": "Input-only inverted-line pin of differential pair L06 in Bank 0 with no output structure or differential termination."+      },+      {+        "number": "176",+        "name": "VCCO_0",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "177",+        "name": "IO_L07P_0/GCLK4",+        "type": "bidirectional",+        "description": "Global clock input GCLK4 that is also a differential true-line user I/O in Bank 0."+      },+      {+        "number": "178",+        "name": "IO_L07N_0/GCLK5",+        "type": "bidirectional",+        "description": "Global clock input GCLK5 that is also a differential inverted-line user I/O in Bank 0."+      },+      {+        "number": "179",+        "name": "IO/VREF_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "180",+        "name": "IO_L08P_0/GCLK6",+        "type": "bidirectional",+        "description": "Global clock input GCLK6 that is also a differential true-line user I/O in Bank 0."+      },+      {+        "number": "181",+        "name": "IO_L08N_0/GCLK7",+        "type": "bidirectional",+        "description": "Global clock input GCLK7 that is also a differential inverted-line user I/O in Bank 0."+      },+      {+        "number": "182",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "183",+        "name": "IP_L09P_0/GCLK8",+        "type": "bidirectional",+        "description": "Global clock input GCLK8 that is also a differential true-line pin in Bank 0."+      },+      {+        "number": "184",+        "name": "IP_L09N_0/GCLK9",+        "type": "bidirectional",+        "description": "Global clock input GCLK9 that is also a differential inverted-line pin in Bank 0."+      },+      {+        "number": "185",+        "name": "IO_L10P_0/GCLK10",+        "type": "bidirectional",+        "description": "Global clock input GCLK10 that is also a differential true-line user I/O in Bank 0."+      },+      {+        "number": "186",+        "name": "IO_L10N_0/GCLK11",+        "type": "bidirectional",+        "description": "Global clock input GCLK11 that is also a differential inverted-line user I/O in Bank 0."+      },+      {+        "number": "187",+        "name": "IO",+        "type": "bidirectional",+        "description": "Unrestricted general-purpose user I/O in Bank 0."+      },+      {+        "number": "188",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "189",+        "name": "IO_L11P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L11 true line in Bank 0."+      },+      {+        "number": "190",+        "name": "IO_L11N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L11 inverted line in Bank 0."+      },+      {+        "number": "191",+        "name": "VCCO_0",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "192",+        "name": "IO_L12P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L12 true line in Bank 0."+      },+      {+        "number": "193",+        "name": "IO_L12N_0/VREF_0",+        "type": "bidirectional",+        "description": "Differential pair L12 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "194",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "195",+        "name": "VCCAUX",+        "type": "power_in",+        "description": "Auxiliary supply pin that must be connected to +2.5V."+      },+      {+        "number": "196",+        "name": "IO_L13P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 true line in Bank 0."+      },+      {+        "number": "197",+        "name": "IO_L13N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L13 inverted line in Bank 0."+      },+      {+        "number": "198",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      },+      {+        "number": "199",+        "name": "IO_L14P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L14 true line in Bank 0."+      },+      {+        "number": "200",+        "name": "IO_L14N_0/VREF_0",+        "type": "bidirectional",+        "description": "Differential pair L14 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used."+      },+      {+        "number": "201",+        "name": "VCCO_0",+        "type": "power_in",+        "description": "Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage."+      },+      {+        "number": "202",+        "name": "IO_L15P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L15 true line in Bank 0."+      },+      {+        "number": "203",+        "name": "IO_L15N_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L15 inverted line in Bank 0."+      },+      {+        "number": "204",+        "name": "IP",+        "type": "input",+        "description": "Input-only pin with no output structure, differential termination resistor, or PCI clamp diode."+      },+      {+        "number": "205",+        "name": "IO_L16P_0",+        "type": "bidirectional",+        "description": "General-purpose user I/O, differential pair L16 true line in Bank 0."+      },+      {+        "number": "206",+        "name": "IO_L16N_0/HSWAP",+        "type": "bidirectional",+        "description": "Dual-purpose HSWAP pin: Low enables pull-up resistors on all user I/O during configuration, High disables them; then a user I/O."+      },+      {+        "number": "207",+        "name": "TDI",+        "type": "input",+        "description": "Dedicated JTAG test data input, powered by VCCAUX."+      },+      {+        "number": "208",+        "name": "GND",+        "type": "power_in",+        "description": "Ground return pin; all GND pins must be connected."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The datasheet tabulates the PQ208 pinout (Table 140, labeled PQ208 / PQG208 package family). The ord; Table 140 lists pin names for the XC3S250E and XC3S500E together (identical footprint); the names ab; Per-pin descriptions are not individually written in the datasheet. They were composed from the pin-",+          "79/208 pins cited to the wrong page (name found elsewhere): ['55:IO_L01P_2/CSO_B@p181', '60:IO_L03P_2/DOUT/BUSY@p181', '61:IO_L03N_2/MOSI/CSI_B@p181', '62:IO_L04P_2@p181']"+        ],+        "pages_sent": 94,+        "cost_usd": 0.8727,+        "at": "2026-10-21T01:50:50"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590226762702888960",+        "pages": 227,+        "sha256": "9ef8122f74a48461",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 208,+        "described": 208,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "xc3s500e-4pqg208c.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          30.93,+          30.93,+          1.6+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "6b5c689015c2fe4ec3afe0ef6e3f9325182a25b05257e4722c7b62133a27ecc8",+        "checked": "2026-10-21",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "xc3s500e-4pqg208c-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          30.93,+          30.93,+          1.6+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "6c501ded5c661dd98769e742bdbfc9352f6db5dd0381b59fe0ddbc2190e41faa",+        "checked": "2026-10-21",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file

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@@ -0,0 +1,1590 @@+(footprint "PQFP-208_28x28mm_P0.5mm"+	(version 20260206)+	(generator "kicad-footprint-generator")+	(layer "F.Cu")+	(descr "PQFP, 208 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095)")+	(tags "PQFP QFP")+	(property "Reference" "REF**"+		(at 0 -16.65 0)+		(layer "F.SilkS")+		(effects+			(font+				(size 1 1)+				(thickness 0.15)+			)+		)+	)+	(property "Value" "PQFP-208_28x28mm_P0.5mm"+		(at 0 16.65 0)+		(layer "F.Fab")+		(effects+			(font+				(size 1 1)+				(thickness 0.15)+			)+		)+	)+	(property "KiLib_Generator" "package/gullwing"+		(at 0 0 0)+		(layer "F.SilkS")+		(hide yes)+		(effects+			(font+				(size 1 1)+				(thickness 0.15)+			)+		)+	)+	(attr smd)+	(duplicate_pad_numbers_are_jumpers no)+	(fp_line+		(start -14.11 -14.11)+		(end -13.16 -14.11)+		(stroke+			(width 0.12)+			(type solid)+		)+		(layer "F.SilkS")+	)+	(fp_line+		(start -14.11 -13.16)+		(end -14.11 -14.11)+		(stroke+			(width 0.12)+			(type solid)+		)+		(layer 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