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XC3S500E-4PQG208C

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AMD XILINX Programmable Logic Device (CPLDs/FPGAs), PQFP-208. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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XC3S500E-4PQG208C

AMD XILINX · Programmable Logic Device (CPLDs/FPGAs) · PQFP-208

XC3S500E-4PQG208C from AMD XILINX, in a PQFP-208. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PROG_B input Active-Low program input; asserting it Low for 500 ns or longer restarts configuration, and an external 4.7 kΩ pull-up to 2.5V is recommended.
2 IO_L01P_3 bidirectional Differential pair L01 true-line general-purpose user I/O in Bank 3.
3 IO_L01N_3 bidirectional Differential pair L01 inverted-line general-purpose user I/O in Bank 3.
4 IO_L02P_3 bidirectional Differential pair L02 true-line general-purpose user I/O in Bank 3.
5 IO_L02N_3/VREF_3 bidirectional Differential pair L02 inverted-line user I/O that serves as a VREF input for Bank 3; all VREF pins in the bank must be connected if used as a reference.
6 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
7 VCCAUX power_in Auxiliary supply pin that must be connected to +2.5V.
8 IO_L03P_3 bidirectional Differential pair L03 true-line general-purpose user I/O in Bank 3.
9 IO_L03N_3 bidirectional Differential pair L03 inverted-line general-purpose user I/O in Bank 3.
10 GND power_in Ground return pin; all GND pins must be connected.
11 IO_L04P_3 bidirectional Differential pair L04 true-line general-purpose user I/O in Bank 3.
12 IO_L04N_3 bidirectional Differential pair L04 inverted-line general-purpose user I/O in Bank 3.
13 VCCINT power_in Internal core logic supply pin that must be connected to +1.2V.
14 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
15 IO_L05P_3 bidirectional Differential pair L05 true-line general-purpose user I/O in Bank 3.
16 IO_L05N_3 bidirectional Differential pair L05 inverted-line general-purpose user I/O in Bank 3.
17 GND power_in Ground return pin; all GND pins must be connected.
18 IO_L06P_3 bidirectional Differential pair L06 true-line general-purpose user I/O in Bank 3.
19 IO_L06N_3 bidirectional Differential pair L06 inverted-line general-purpose user I/O in Bank 3.
20 IP/VREF_3 input Input-only pin that is also a VREF input for Bank 3; all VREF pins in the bank must be connected if a reference voltage is used.
21 VCCO_3 power_in Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage.
22 IO_L07P_3/LHCLK0 bidirectional Left-half clock input LHCLK0 that is also a differential true-line user I/O in Bank 3.
23 IO_L07N_3/LHCLK1 bidirectional Left-half clock input LHCLK1 that is also a differential inverted-line user I/O in Bank 3.
24 IO_L08P_3/LHCLK2 bidirectional Left-half clock input LHCLK2 that is also a differential true-line user I/O in Bank 3.
25 IO_L08N_3/LHCLK3 bidirectional Left-half clock input LHCLK3 that is also a differential inverted-line user I/O in Bank 3.
26 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
27 GND power_in Ground return pin; all GND pins must be connected.
28 IO_L09P_3/LHCLK4 bidirectional Left-half clock input LHCLK4 that is also a differential true-line user I/O in Bank 3.
29 IO_L09N_3/LHCLK5 bidirectional Left-half clock input LHCLK5 that is also a differential inverted-line user I/O in Bank 3.
30 IO_L10P_3/LHCLK6 bidirectional Left-half clock input LHCLK6 that is also a differential true-line user I/O in Bank 3.
31 IO_L10N_3/LHCLK7 bidirectional Left-half clock input LHCLK7 that is also a differential inverted-line user I/O in Bank 3.
32 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
33 IO_L11P_3 bidirectional Differential pair L11 true-line general-purpose user I/O in Bank 3.
34 IO_L11N_3 bidirectional Differential pair L11 inverted-line general-purpose user I/O in Bank 3.
35 IO_L12P_3 bidirectional Differential pair L12 true-line general-purpose user I/O in Bank 3.
36 IO_L12N_3 bidirectional Differential pair L12 inverted-line general-purpose user I/O in Bank 3.
37 GND power_in Ground return pin; all GND pins must be connected.
38 VCCO_3 power_in Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage.
39 IO_L13P_3 bidirectional Differential pair L13 true-line general-purpose user I/O in Bank 3.
40 IO_L13N_3 bidirectional Differential pair L13 inverted-line general-purpose user I/O in Bank 3.
41 IO_L14P_3 bidirectional Differential pair L14 true-line general-purpose user I/O in Bank 3.
42 IO_L14N_3 bidirectional Differential pair L14 inverted-line general-purpose user I/O in Bank 3.
43 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
44 VCCAUX power_in Auxiliary supply pin that must be connected to +2.5V.
45 IO/VREF_3 bidirectional General-purpose user I/O that is also a VREF reference input for Bank 3; all VREF pins in the bank must be connected if used.
46 VCCO_3 power_in Output-buffer supply for Bank 3; all VCCO pins of the bank must be connected to the same voltage.
47 IO_L15P_3 bidirectional Differential pair L15 true-line general-purpose user I/O in Bank 3.
48 IO_L15N_3 bidirectional Differential pair L15 inverted-line general-purpose user I/O in Bank 3.
49 IO_L16P_3 bidirectional Differential pair L16 true-line general-purpose user I/O in Bank 3.
50 IO_L16N_3 bidirectional Differential pair L16 inverted-line general-purpose user I/O in Bank 3.
51 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
52 GND power_in Ground return pin; all GND pins must be connected.
53 GND power_in Ground return pin; all GND pins must be connected.
54 IP input Input-only pin in Bank 2 with no output structure, differential termination resistor, or PCI clamp diode.
55 IO_L01P_2/CSO_B bidirectional Dual-purpose CSO_B chip-select output (Active Low) during configuration, then a user I/O after configuration.
56 IO_L01N_2/INIT_B bidirectional Open-drain INIT_B initialization indicator (Active Low) during configuration; drive High if unused as user I/O.
57 IP_L02P_2 input Input-only true-line pin of differential pair L02 in Bank 2; on-chip differential termination is not available on dedicated inputs.
58 IP_L02N_2 input Input-only inverted-line pin of differential pair L02 in Bank 2; on-chip differential termination is not available on dedicated inputs.
59 VCCO_2 power_in Output-buffer supply for Bank 2, which must match the configuration source voltage and is an input to the Power-On Reset circuit.
60 IO_L03P_2/DOUT/BUSY bidirectional Dual-purpose DOUT/BUSY pin that drives daisy-chain serial data or BUSY status during configuration, then is a user I/O.
61 IO_L03N_2/MOSI/CSI_B bidirectional Dual-purpose MOSI (SPI) or CSI_B chip-select input (must be Low throughout parallel configuration), then a user I/O.
62 IO_L04P_2 bidirectional General-purpose user I/O, differential pair L04 true line in Bank 2.
63 IO_L04N_2 bidirectional General-purpose user I/O, differential pair L04 inverted line in Bank 2.
64 IO_L05P_2 bidirectional General-purpose user I/O, differential pair L05 true line in Bank 2.
65 IO_L05N_2 bidirectional General-purpose user I/O, differential pair L05 inverted line in Bank 2.
66 VCCAUX power_in Auxiliary supply pin that must be connected to +2.5V.
67 VCCINT power_in Internal core logic supply pin that must be connected to +1.2V.
68 IO_L06P_2 bidirectional General-purpose user I/O, differential pair L06 true line in Bank 2.
69 IO_L06N_2 bidirectional General-purpose user I/O, differential pair L06 inverted line in Bank 2.
70 GND power_in Ground return pin; all GND pins must be connected.
71 IP_L07P_2 input Input-only true-line pin of differential pair L07 in Bank 2.
72 IP_L07N_2/VREF_2 input Input-only inverted-line pin that is also a VREF input for Bank 2; all VREF pins in the bank must be connected if used.
73 VCCO_2 power_in Output-buffer supply for Bank 2; all VCCO pins of the bank must be connected to the same voltage.
74 IO_L08P_2/D7/GCLK12 bidirectional Dual-purpose D7 configuration data bit and global clock input GCLK12, usable as user I/O after configuration.
75 IO_L08N_2/D6/GCLK13 bidirectional Dual-purpose D6 configuration data bit and global clock input GCLK13, usable as user I/O after configuration.
76 IO/D5 bidirectional Dual-purpose D5 configuration data bit used in parallel modes, then a user I/O.
77 IO_L09P_2/D4/GCLK14 bidirectional Dual-purpose D4 configuration data bit and global clock input GCLK14, usable as user I/O after configuration.
78 IO_L09N_2/D3/GCLK15 bidirectional Dual-purpose D3 configuration data bit and global clock input GCLK15, usable as user I/O after configuration.
79 GND power_in Ground return pin; all GND pins must be connected.
80 IP_L10P_2/RDWR_B/GCLK0 bidirectional Dual-purpose RDWR_B read/write control (must be Low during configuration) and global clock input GCLK0.
81 IP_L10N_2/M2/GCLK1 bidirectional Dual-purpose M2 mode-select pin sampled when INIT_B goes High, shared with global clock input GCLK1 (design note: avoid using GCLK1 as a clock).
82 IO_L11P_2/D2/GCLK2 bidirectional Dual-purpose D2 configuration data bit and global clock input GCLK2, usable as user I/O after configuration.
83 IO_L11N_2/D1/GCLK3 bidirectional Dual-purpose D1 configuration data bit and global clock input GCLK3, usable as user I/O after configuration.
84 IO/M1 input Dual-purpose M1 mode-select pin that must be at a defined level when INIT_B goes High, then a user I/O.
85 GND power_in Ground return pin; all GND pins must be connected.
86 IO_L12P_2/M0 input Dual-purpose M0 mode-select pin that must be at a defined level when INIT_B goes High, then a user I/O.
87 IO_L12N_2/DIN/D0 input Dual-purpose DIN/D0 serial configuration data input, then a user I/O after configuration.
88 VCCO_2 power_in Output-buffer supply for Bank 2; all VCCO pins of the bank must be connected to the same voltage.
89 IO_L13P_2 bidirectional General-purpose user I/O, differential pair L13 true line in Bank 2.
90 IO_L13N_2 bidirectional General-purpose user I/O, differential pair L13 inverted line in Bank 2.
91 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
92 VCCAUX power_in Auxiliary supply pin that must be connected to +2.5V.
93 IO_L14P_2/A23 bidirectional Dual-purpose BPI address line A23 used in parallel Flash configuration, then a user I/O.
94 IO_L14N_2/A22 bidirectional Dual-purpose BPI address line A22 used in parallel Flash configuration, then a user I/O.
95 GND power_in Ground return pin; all GND pins must be connected.
96 IO_L15P_2/A21 bidirectional Dual-purpose BPI address line A21 used in parallel Flash configuration, then a user I/O.
97 IO_L15N_2/A20 bidirectional Dual-purpose BPI address line A20 used in parallel Flash configuration, then a user I/O.
98 IO/VREF_2 bidirectional General-purpose user I/O that is also a VREF input for Bank 2; all VREF pins in the bank must be connected if used.
99 IO_L16P_2/VS2/A19 bidirectional Dual-purpose SPI variant-select VS2 (sampled when INIT_B goes High) and BPI address line A19, then a user I/O.
100 IO_L16N_2/VS1/A18 bidirectional Dual-purpose SPI variant-select VS1 (sampled when INIT_B goes High) and BPI address line A18, then a user I/O.
101 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
102 IO_L17P_2/VS0/A17 bidirectional Dual-purpose SPI variant-select VS0 (sampled when INIT_B goes High) and BPI address line A17, then a user I/O.
103 IO_L17N_2/CCLK bidirectional Dual-purpose configuration clock CCLK, driven by the FPGA in master modes and an input in slave modes, then a user I/O.
104 DONE bidirectional Open-drain configuration DONE indicator that goes High when configuration completes and requires an external 330 Ω pull-up to 2.5V.
105 GND power_in Ground return pin; all GND pins must be connected.
106 IO_L01P_1/A16 bidirectional Dual-purpose BPI address line A16 used in parallel Flash configuration, then a user I/O (differential pair L01 true line).
107 IO_L01N_1/A15 bidirectional Dual-purpose BPI address line A15 used in parallel Flash configuration, then a user I/O (differential pair L01 inverted line).
108 IO_L02P_1/A14 bidirectional Dual-purpose BPI address line A14 used in parallel Flash configuration, then a user I/O (differential pair L02 true line).
109 IO_L02N_1/A13 bidirectional Dual-purpose BPI address line A13 used in parallel Flash configuration, then a user I/O (differential pair L02 inverted line).
110 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
111 VCCAUX power_in Auxiliary supply pin that must be connected to +2.5V.
112 IO_L03P_1 bidirectional General-purpose user I/O, differential pair L03 true line in Bank 1.
113 IO_L03N_1/VREF_1 bidirectional Differential pair L03 inverted-line user I/O that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used.
114 VCCO_1 power_in Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage.
115 IO_L04P_1 bidirectional General-purpose user I/O, differential pair L04 true line in Bank 1.
116 IO_L04N_1 bidirectional General-purpose user I/O, differential pair L04 inverted line in Bank 1.
117 VCCINT power_in Internal core logic supply pin that must be connected to +1.2V.
118 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
119 IO_L05P_1/A12 bidirectional Dual-purpose BPI address line A12 used in parallel Flash configuration, then a user I/O (differential pair L05 true line).
120 IO_L05N_1/A11 bidirectional Dual-purpose BPI address line A11 used in parallel Flash configuration, then a user I/O (differential pair L05 inverted line).
121 GND power_in Ground return pin; all GND pins must be connected.
122 IO_L06P_1 bidirectional General-purpose user I/O, differential pair L06 true line in Bank 1.
123 IO_L06N_1/VREF_1 bidirectional Differential pair L06 inverted-line user I/O that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used.
124 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
125 VCCO_1 power_in Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage.
126 IO_L07P_1/A10/RHCLK0 bidirectional Right-half clock input RHCLK0 and dual-purpose BPI address line A10, then a user I/O.
127 IO_L07N_1/A9/RHCLK1 bidirectional Right-half clock input RHCLK1 and dual-purpose BPI address line A9, then a user I/O.
128 IO_L08P_1/A8/RHCLK2 bidirectional Right-half clock input RHCLK2 and dual-purpose BPI address line A8, then a user I/O.
129 IO_L08N_1/A7/RHCLK3 bidirectional Right-half clock input RHCLK3 and dual-purpose BPI address line A7, then a user I/O.
130 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
131 GND power_in Ground return pin; all GND pins must be connected.
132 IO_L09P_1/A6/RHCLK4 bidirectional Right-half clock input RHCLK4 and dual-purpose BPI address line A6, then a user I/O.
133 IO_L09N_1/A5/RHCLK5 bidirectional Right-half clock input RHCLK5 and dual-purpose BPI address line A5, then a user I/O.
134 IO_L10P_1/A4/RHCLK6 bidirectional Right-half clock input RHCLK6 and dual-purpose BPI address line A4, then a user I/O.
135 IO_L10N_1/A3/RHCLK7 bidirectional Right-half clock input RHCLK7 and dual-purpose BPI address line A3, then a user I/O.
136 IP/VREF_1 input Input-only pin that is also a VREF input for Bank 1; all VREF pins in the bank must be connected if used.
137 IO_L11P_1/A2 bidirectional Dual-purpose BPI address line A2 used in parallel Flash configuration, then a user I/O (differential pair L11 true line).
138 IO_L11N_1/A1 bidirectional Dual-purpose BPI address line A1 used in parallel Flash configuration, then a user I/O (differential pair L11 inverted line).
139 IO_L12P_1 bidirectional General-purpose user I/O, differential pair L12 true line in Bank 1.
140 IO_L12N_1/A0 bidirectional Dual-purpose BPI address line A0 used in parallel Flash configuration, then a user I/O (differential pair L12 inverted line).
141 GND power_in Ground return pin; all GND pins must be connected.
142 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
143 VCCO_1 power_in Output-buffer supply for Bank 1; all VCCO pins of the bank must be connected to the same voltage.
144 IO_L13P_1 bidirectional General-purpose user I/O, differential pair L13 true line in Bank 1.
145 IO_L13N_1 bidirectional General-purpose user I/O, differential pair L13 inverted line in Bank 1.
146 IO_L14P_1 bidirectional General-purpose user I/O, differential pair L14 true line in Bank 1.
147 IO_L14N_1 bidirectional General-purpose user I/O, differential pair L14 inverted line in Bank 1.
148 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
149 VCCAUX power_in Auxiliary supply pin that must be connected to +2.5V.
150 IO_L15P_1/HDC bidirectional Dual-purpose HDC parallel Flash write-enable (WE#) output during configuration, then a user I/O.
151 IO_L15N_1/LDC0 bidirectional Dual-purpose LDC0 parallel Flash chip-enable (CE#) output driven Low during configuration, then a user I/O.
152 IO_L16P_1/LDC1 bidirectional Dual-purpose LDC1 parallel Flash output-enable (OE#) driven Low during configuration, then a user I/O.
153 IO_L16N_1/LDC2 bidirectional Dual-purpose LDC2 parallel Flash BYTE# control, driven Low during configuration, then a user I/O.
154 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
155 TMS input Dedicated JTAG test mode select input, powered by VCCAUX.
156 GND power_in Ground return pin; all GND pins must be connected.
157 TDO output Dedicated JTAG test data output, powered by VCCAUX.
158 TCK input Dedicated JTAG test clock input, powered by VCCAUX.
159 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
160 IO_L01P_0 bidirectional General-purpose user I/O, differential pair L01 true line in Bank 0.
161 IO_L01N_0 bidirectional General-purpose user I/O, differential pair L01 inverted line in Bank 0.
162 IO_L02P_0 bidirectional General-purpose user I/O, differential pair L02 true line in Bank 0.
163 IO_L02N_0/VREF_0 bidirectional Differential pair L02 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used.
164 IO_L03P_0 bidirectional General-purpose user I/O, differential pair L03 true line in Bank 0.
165 IO_L03N_0 bidirectional General-purpose user I/O, differential pair L03 inverted line in Bank 0.
166 VCCAUX power_in Auxiliary supply pin that must be connected to +2.5V.
167 IO_L04P_0 bidirectional General-purpose user I/O, differential pair L04 true line in Bank 0.
168 IO_L04N_0/VREF_0 bidirectional Differential pair L04 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used.
169 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
170 VCCINT power_in Internal core logic supply pin that must be connected to +1.2V.
171 IO_L05P_0 bidirectional General-purpose user I/O, differential pair L05 true line in Bank 0.
172 IO_L05N_0 bidirectional General-purpose user I/O, differential pair L05 inverted line in Bank 0.
173 GND power_in Ground return pin; all GND pins must be connected.
174 IP_L06P_0 input Input-only true-line pin of differential pair L06 in Bank 0 with no output structure or differential termination.
175 IP_L06N_0 input Input-only inverted-line pin of differential pair L06 in Bank 0 with no output structure or differential termination.
176 VCCO_0 power_in Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage.
177 IO_L07P_0/GCLK4 bidirectional Global clock input GCLK4 that is also a differential true-line user I/O in Bank 0.
178 IO_L07N_0/GCLK5 bidirectional Global clock input GCLK5 that is also a differential inverted-line user I/O in Bank 0.
179 IO/VREF_0 bidirectional General-purpose user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used.
180 IO_L08P_0/GCLK6 bidirectional Global clock input GCLK6 that is also a differential true-line user I/O in Bank 0.
181 IO_L08N_0/GCLK7 bidirectional Global clock input GCLK7 that is also a differential inverted-line user I/O in Bank 0.
182 GND power_in Ground return pin; all GND pins must be connected.
183 IP_L09P_0/GCLK8 bidirectional Global clock input GCLK8 that is also a differential true-line pin in Bank 0.
184 IP_L09N_0/GCLK9 bidirectional Global clock input GCLK9 that is also a differential inverted-line pin in Bank 0.
185 IO_L10P_0/GCLK10 bidirectional Global clock input GCLK10 that is also a differential true-line user I/O in Bank 0.
186 IO_L10N_0/GCLK11 bidirectional Global clock input GCLK11 that is also a differential inverted-line user I/O in Bank 0.
187 IO bidirectional Unrestricted general-purpose user I/O in Bank 0.
188 GND power_in Ground return pin; all GND pins must be connected.
189 IO_L11P_0 bidirectional General-purpose user I/O, differential pair L11 true line in Bank 0.
190 IO_L11N_0 bidirectional General-purpose user I/O, differential pair L11 inverted line in Bank 0.
191 VCCO_0 power_in Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage.
192 IO_L12P_0 bidirectional General-purpose user I/O, differential pair L12 true line in Bank 0.
193 IO_L12N_0/VREF_0 bidirectional Differential pair L12 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used.
194 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
195 VCCAUX power_in Auxiliary supply pin that must be connected to +2.5V.
196 IO_L13P_0 bidirectional General-purpose user I/O, differential pair L13 true line in Bank 0.
197 IO_L13N_0 bidirectional General-purpose user I/O, differential pair L13 inverted line in Bank 0.
198 GND power_in Ground return pin; all GND pins must be connected.
199 IO_L14P_0 bidirectional General-purpose user I/O, differential pair L14 true line in Bank 0.
200 IO_L14N_0/VREF_0 bidirectional Differential pair L14 inverted-line user I/O that is also a VREF input for Bank 0; all VREF pins in the bank must be connected if used.
201 VCCO_0 power_in Output-buffer supply for Bank 0; all VCCO pins of the bank must be connected to the same voltage.
202 IO_L15P_0 bidirectional General-purpose user I/O, differential pair L15 true line in Bank 0.
203 IO_L15N_0 bidirectional General-purpose user I/O, differential pair L15 inverted line in Bank 0.
204 IP input Input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
205 IO_L16P_0 bidirectional General-purpose user I/O, differential pair L16 true line in Bank 0.
206 IO_L16N_0/HSWAP bidirectional Dual-purpose HSWAP pin: Low enables pull-up resistors on all user I/O during configuration, High disables them; then a user I/O.
207 TDI input Dedicated JTAG test data input, powered by VCCAUX.
208 GND power_in Ground return pin; all GND pins must be connected.

Key specifications

Parameter Value
Manufacturer AMD XILINX
Package PQFP-208
Category Embedded Processors & Controllers
Pins 208

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature range (TJ), Commercial grade TJ 0 85 °C Commercial (C) grade, as in ordering information 6
Clock-to-output time, with DCM (TICKOFDCM), XC3S500E -4 TICKOFDCM 3.46 ns LVCMOS25, 12 mA output drive, Fast slew rate, with DCM 125
Clock-to-output time, without DCM (TICKOF), XC3S500E -4 TICKOF 5.51 ns LVCMOS25, 12 mA output drive, Fast slew rate, without DCM 125
Setup time to IFF with DCM (TPSDCM), XC3S500E -4 TPSDCM 2.59 ns LVCMOS25, IFD_DELAY_VALUE = 0, with DCM 126
Setup time to IFF without DCM (TPSFD), XC3S500E -4 TPSFD 4.73 ns LVCMOS25, IFD_DELAY_VALUE = default software setting (delay value 3) 126
Hold time to IFF with DCM (TPHDCM), XC3S500E -4 TPHDCM 0.14 ns LVCMOS25, IFD_DELAY_VALUE = 0, with DCM 126
Hold time to IFF without DCM (TPHFD), XC3S500E -4 TPHFD -0.77 ns LVCMOS25, IFD_DELAY_VALUE = default software setting (delay value 3) 126
Frequency of CCLK input, no bitstream compression, not using BUSY pin FCCPAR 0 50 MHz No bitstream compression; not using the BUSY pin 149
Frequency of CCLK input, no bitstream compression, using BUSY pin FCCPAR 0 66 MHz No bitstream compression; using the BUSY pin 149
Frequency of CCLK input, with bitstream compression FCCPAR 0 20 MHz With bitstream compression 149
High pulse width at CCLK input pin TCCH 5 ns 149
Low pulse width at CCLK input pin TCCL 5 ns 149
On-chip differential input termination 120 Ω Across differential receiver terminals; available only in banks with VCCO = 2.5V 17

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Dedicated pins(6) -0.5, VCCAUX + 0.5 V TIN Input signal transition time(7), - 500 ns 117

CAD (KiCad official)

  • Symbol: XC3S500E-4PQG208C
  • Footprint: Package_QFP:PQFP-208_28x28mm_P0.5mm
  • 3D model: PQFP-208 (KiCad packages3D, STEP)
  • 3D model files: xc3s500e-4pqg208c-etched.step / xc3s500e-4pqg208c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xc3s500e-4pqg208c.step / xc3s500e-4pqg208c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AMD XILINX datasheet (227 pp, sha256 9ef8122f74a48461, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF