component
XC3S100E-4TQG144I
Public Made by Adomby adom
XILINX Programmable Logic Device (CPLDs/FPGAs), TQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "xc3s100e-4tqg144i",
"version": "0.1.0",
"type": "component",
"description": "XILINX Programmable Logic Device (CPLDs/FPGAs), TQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"embedded processors & controllers",
"xc3s100e-4tqg144i",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
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"files": [
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"component": {
"mpn": "XC3S100E-4TQG144I",
"manufacturer": "XILINX",
"package": "TQFP-144(20x20)",
"pin_count": 144,
"category": "Embedded Processors & Controllers",
"subcategory": "Programmable Logic Device (CPLDs/FPGAs)",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590225380184928256",
"parts": {
"symbol": "xc3s100e-4tqg144i.kicad_sym",
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"model_3d_step_plain": "xc3s100e-4tqg144i.step",
"lbr": "xc3s100e-4tqg144i.lbr"
},
"distributor_links": {
"lcsc": "C2976018",
"digikey": "122-1710-ND",
"mouser": "217-C3S100E-4TQG144I"
},
"distributor_check": {
"checked_at": "2026-10-20T23:23:28Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "122-1710-ND",
"status": "found",
"lifecycle": "Obsolete"
},
"mouser": {
"pn": "217-C3S100E-4TQG144I",
"status": "found",
"lifecycle": "End of Life"
}
},
"pins": [
{
"number": "132",
"name": "IO",
"type": "bidirectional",
"description": "Unrestricted, general-purpose user I/O pin in Bank 0."
},
{
"number": "124",
"name": "IO/VREF_0",
"type": "bidirectional",
"description": "User I/O that serves as a VREF reference input for HSTL/SSTL standards in Bank 0; if used for VREF, all VREF pins in the bank must be connected."
},
{
"number": "113",
"name": "IO_L01N_0",
"type": "bidirectional",
"description": "Unrestricted user I/O; the inverted (N) line of differential pair L01 in Bank 0."
},
{
"number": "112",
"name": "IO_L01P_0",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L01 in Bank 0."
},
{
"number": "117",
"name": "IO_L02N_0",
"type": "bidirectional",
"description": "Unrestricted user I/O; the inverted (N) line of differential pair L02 in Bank 0."
},
{
"number": "116",
"name": "IO_L02P_0",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L02 in Bank 0."
},
{
"number": "123",
"name": "IO_L04N_0/GCLK5",
"type": "bidirectional",
"description": "Global clock input GCLK5 (inverted line of pair L04) that can optionally clock the whole device and can also be a user I/O."
},
{
"number": "122",
"name": "IO_L04P_0/GCLK4",
"type": "bidirectional",
"description": "Global clock input GCLK4 (true line of pair L04) that can optionally clock the whole device and can also be a user I/O."
},
{
"number": "126",
"name": "IO_L05N_0/GCLK7",
"type": "bidirectional",
"description": "Global clock input GCLK7 (inverted line of pair L05) that can optionally clock the whole device and can also be a user I/O."
},
{
"number": "125",
"name": "IO_L05P_0/GCLK6",
"type": "bidirectional",
"description": "Global clock input GCLK6 (true line of pair L05) that can optionally clock the whole device and can also be a user I/O."
},
{
"number": "131",
"name": "IO_L07N_0/GCLK11",
"type": "bidirectional",
"description": "Global clock input GCLK11 (inverted line of pair L07) that can optionally clock the whole device and can also be a user I/O."
},
{
"number": "130",
"name": "IO_L07P_0/GCLK10",
"type": "bidirectional",
"description": "Global clock input GCLK10 (true line of pair L07) that can optionally clock the whole device and can also be a user I/O."
},
{
"number": "135",
"name": "IO_L08N_0/VREF_0",
"type": "bidirectional",
"description": "User I/O that serves as a VREF reference input for HSTL/SSTL standards in Bank 0; if used for VREF, all VREF pins in the bank must be connected."
},
{
"number": "134",
"name": "IO_L08P_0",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L08 in Bank 0."
},
{
"number": "140",
"name": "IO_L09N_0",
"type": "bidirectional",
"description": "Unrestricted user I/O; the inverted (N) line of differential pair L09 in Bank 0."
},
{
"number": "139",
"name": "IO_L09P_0",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L09 in Bank 0."
},
{
"number": "143",
"name": "IO_L10N_0/HSWAP",
"type": "bidirectional",
"description": "Dual-purpose HSWAP pin: when Low during configuration it enables pull-up resistors on all I/O pins to their VCCO, and it must stay at a constant logic level throughout configuration."
},
{
"number": "142",
"name": "IO_L10P_0",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L10 in Bank 0."
},
{
"number": "111",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "114",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "136",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "141",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "120",
"name": "IP_L03N_0",
"type": "input",
"description": "Input-only inverted (N) line of differential pair L03 in Bank 0, with no output structure."
},
{
"number": "119",
"name": "IP_L03P_0",
"type": "input",
"description": "Input-only true (P) line of differential pair L03 in Bank 0, with no output structure."
},
{
"number": "129",
"name": "IP_L06N_0/GCLK9",
"type": "input",
"description": "Input-only global clock input GCLK9 (inverted line of pair L06) that optionally clocks the entire device."
},
{
"number": "128",
"name": "IP_L06P_0/GCLK8",
"type": "input",
"description": "Input-only global clock input GCLK8 (true line of pair L06) that optionally clocks the entire device."
},
{
"number": "121",
"name": "VCCO_0",
"type": "power_in",
"description": "Output-driver supply for Bank 0 (top edge); all VCCO_0 pins must be connected to the same voltage (3.3V, 2.5V, 1.8V, 1.5V or 1.2V)."
},
{
"number": "138",
"name": "VCCO_0",
"type": "power_in",
"description": "Output-driver supply for Bank 0 (top edge); all VCCO_0 pins must be connected to the same voltage (3.3V, 2.5V, 1.8V, 1.5V or 1.2V)."
},
{
"number": "98",
"name": "IO/A0",
"type": "bidirectional",
"description": "Dual-purpose address output A0 in BPI parallel Flash configuration mode; becomes a user I/O after configuration."
},
{
"number": "83",
"name": "IO/VREF_1",
"type": "bidirectional",
"description": "User I/O that serves as a VREF reference input in Bank 1; if used for VREF, all VREF pins in the bank must be connected."
},
{
"number": "75",
"name": "IO_L01N_1/A15",
"type": "bidirectional",
"description": "Dual-purpose address output A15 in BPI mode and user I/O after configuration; inverted line of differential pair L01 in Bank 1."
},
{
"number": "74",
"name": "IO_L01P_1/A16",
"type": "bidirectional",
"description": "Dual-purpose address output A16 in BPI mode and user I/O after configuration; true line of differential pair L01 in Bank 1."
},
{
"number": "77",
"name": "IO_L02N_1/A13",
"type": "bidirectional",
"description": "Dual-purpose address output A13 in BPI mode and user I/O after configuration; inverted line of differential pair L02 in Bank 1."
},
{
"number": "76",
"name": "IO_L02P_1/A14",
"type": "bidirectional",
"description": "Dual-purpose address output A14 in BPI mode and user I/O after configuration; true line of differential pair L02 in Bank 1."
},
{
"number": "82",
"name": "IO_L03N_1/A11",
"type": "bidirectional",
"description": "Dual-purpose address output A11 in BPI mode and user I/O after configuration; inverted line of differential pair L03 in Bank 1."
},
{
"number": "81",
"name": "IO_L03P_1/A12",
"type": "bidirectional",
"description": "Dual-purpose address output A12 in BPI mode and user I/O after configuration; true line of differential pair L03 in Bank 1."
},
{
"number": "86",
"name": "IO_L04N_1/A9/RHCLK1",
"type": "bidirectional",
"description": "Right-half clock input RHCLK1 that also carries dual-purpose address output A9 in BPI mode; can be a user I/O."
},
{
"number": "85",
"name": "IO_L04P_1/A10/RHCLK0",
"type": "bidirectional",
"description": "Right-half clock input RHCLK0 that also carries dual-purpose address output A10 in BPI mode; can be a user I/O."
},
{
"number": "88",
"name": "IO_L05N_1/A7/RHCLK3/TRDY1",
"type": "bidirectional",
"description": "Right-half clock input RHCLK3 with dual-purpose address output A7 in BPI mode and the TRDY1 PCI function; can be a user I/O."
},
{
"number": "87",
"name": "IO_L05P_1/A8/RHCLK2",
"type": "bidirectional",
"description": "Right-half clock input RHCLK2 that also carries dual-purpose address output A8 in BPI mode; can be a user I/O."
},
{
"number": "92",
"name": "IO_L06N_1/A5/RHCLK5",
"type": "bidirectional",
"description": "Right-half clock input RHCLK5 that also carries dual-purpose address output A5 in BPI mode; can be a user I/O."
},
{
"number": "91",
"name": "IO_L06P_1/A6/RHCLK4/IRDY1",
"type": "bidirectional",
"description": "Right-half clock input RHCLK4 with dual-purpose address output A6 in BPI mode and the IRDY1 PCI function; can be a user I/O."
},
{
"number": "94",
"name": "IO_L07N_1/A3/RHCLK7",
"type": "bidirectional",
"description": "Right-half clock input RHCLK7 that also carries dual-purpose address output A3 in BPI mode; can be a user I/O."
},
{
"number": "93",
"name": "IO_L07P_1/A4/RHCLK6",
"type": "bidirectional",
"description": "Right-half clock input RHCLK6 that also carries dual-purpose address output A4 in BPI mode; can be a user I/O."
},
{
"number": "97",
"name": "IO_L08N_1/A1",
"type": "bidirectional",
"description": "Dual-purpose address output A1 in BPI mode and user I/O after configuration; inverted line of differential pair L08 in Bank 1."
},
{
"number": "96",
"name": "IO_L08P_1/A2",
"type": "bidirectional",
"description": "Dual-purpose address output A2 in BPI mode and user I/O after configuration; true line of differential pair L08 in Bank 1."
},
{
"number": "104",
"name": "IO_L09N_1/LDC0",
"type": "bidirectional",
"description": "Dual-purpose LDC0, the BPI PROM chip-select (CE#) output driven Low during configuration; user I/O after configuration."
},
{
"number": "103",
"name": "IO_L09P_1/HDC",
"type": "bidirectional",
"description": "Dual-purpose HDC, the BPI PROM write-enable (WE#) output driven High throughout configuration; user I/O after configuration."
},
{
"number": "106",
"name": "IO_L10N_1/LDC2",
"type": "bidirectional",
"description": "Dual-purpose LDC2, the BPI PROM byte-mode (BYTE#) control driven Low during configuration; user I/O after configuration."
},
{
"number": "105",
"name": "IO_L10P_1/LDC1",
"type": "bidirectional",
"description": "Dual-purpose LDC1, the BPI PROM output-enable (OE#) control driven Low during configuration; user I/O after configuration."
},
{
"number": "78",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "84",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "89",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "101",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "107",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "95",
"name": "IP/VREF_1",
"type": "input",
"description": "Input-only pin that serves as the VREF reference input for Bank 1 when a bank standard requires it."
},
{
"number": "79",
"name": "VCCO_1",
"type": "power_in",
"description": "Output-driver supply for Bank 1 (right edge); all VCCO_1 pins must be connected to the same voltage."
},
{
"number": "100",
"name": "VCCO_1",
"type": "power_in",
"description": "Output-driver supply for Bank 1 (right edge); all VCCO_1 pins must be connected to the same voltage."
},
{
"number": "52",
"name": "IO/D5",
"type": "bidirectional",
"description": "Dual-purpose D5 data input for byte-wide parallel configuration; becomes a user I/O after configuration."
},
{
"number": "60",
"name": "IO/M1",
"type": "bidirectional",
"description": "Dual-purpose M1 configuration mode-select pin, sampled when INIT_B goes High; becomes a user I/O after configuration."
},
{
"number": "66",
"name": "IP/VREF_2",
"type": "input",
"description": "Input-only VREF pin for Bank 2 on the XC3S100E (VREF(I/O) on the XC3S250E); if used for VREF, all VREF pins in the bank must be connected."
},
{
"number": "40",
"name": "IO_L01N_2/INIT_B",
"type": "bidirectional",
"description": "Open-drain INIT_B initialization indicator, active Low; requires an external 4.7 kΩ pull-up to VCCO_2 in daisy-chain applications, and becomes a user I/O after configuration."
},
{
"number": "39",
"name": "IO_L01P_2/CSO_B",
"type": "bidirectional",
"description": "Chip-select output CSO_B, active Low, used in SPI and BPI configuration modes; becomes a user I/O after configuration."
},
{
"number": "44",
"name": "IO_L02N_2/MOSI/CSI_B",
"type": "bidirectional",
"description": "Dual-purpose MOSI serial data output in SPI mode or CSI_B chip-select input in parallel modes (must be Low throughout configuration)."
},
{
"number": "43",
"name": "IO_L02P_2/DOUT/BUSY",
"type": "bidirectional",
"description": "Dual-purpose DOUT serial data output for daisy-chains or BUSY in parallel modes; BUSY must be monitored when CCLK exceeds 50 MHz."
},
{
"number": "51",
"name": "IO_L04N_2/D6/GCLK13",
"type": "bidirectional",
"description": "Dual-purpose D6 data input in parallel configuration modes and global clock input GCLK13; can be a user I/O."
},
{
"number": "50",
"name": "IO_L04P_2/D7/GCLK12",
"type": "bidirectional",
"description": "Dual-purpose D7 data input in parallel configuration modes and global clock input GCLK12; can be a user I/O."
},
{
"number": "54",
"name": "IO_L05N_2/D3/GCLK15",
"type": "bidirectional",
"description": "Dual-purpose D3 data input in parallel configuration modes and global clock input GCLK15; can be a user I/O."
},
{
"number": "53",
"name": "IO_L05P_2/D4/GCLK14",
"type": "bidirectional",
"description": "Dual-purpose D4 data input in parallel configuration modes and global clock input GCLK14; can be a user I/O."
},
{
"number": "59",
"name": "IO_L07N_2/D1/GCLK3",
"type": "bidirectional",
"description": "Dual-purpose D1 data input in parallel configuration modes and global clock input GCLK3; can be a user I/O."
},
{
"number": "58",
"name": "IO_L07P_2/D2/GCLK2",
"type": "bidirectional",
"description": "Dual-purpose D2 data input in parallel configuration modes and global clock input GCLK2; can be a user I/O."
},
{
"number": "63",
"name": "IO_L08N_2/DIN/D0",
"type": "bidirectional",
"description": "Dual-purpose serial data input DIN in serial modes or D0 parallel data input; becomes a user I/O after configuration."
},
{
"number": "62",
"name": "IO_L08P_2/M0",
"type": "bidirectional",
"description": "Dual-purpose M0 mode-select pin, sampled when INIT_B goes High; becomes a user I/O after configuration."
},
{
"number": "68",
"name": "IO_L09N_2/VS1/A18",
"type": "bidirectional",
"description": "Dual-purpose VS1 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A18 in BPI mode."
},
{
"number": "67",
"name": "IO_L09P_2/VS2/A19",
"type": "bidirectional",
"description": "Dual-purpose VS2 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A19 in BPI mode."
},
{
"number": "71",
"name": "IO_L10N_2/CCLK",
"type": "bidirectional",
"description": "Dual-purpose configuration clock: FPGA-generated in master modes and an external clock input in slave modes; becomes a user I/O after configuration."
},
{
"number": "70",
"name": "IO_L10P_2/VS0/A17",
"type": "bidirectional",
"description": "Dual-purpose VS0 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A17 in BPI mode."
},
{
"number": "38",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "41",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "69",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "48",
"name": "IP_L03N_2/VREF_2",
"type": "input",
"description": "Input-only inverted line of pair L03 in Bank 2 that also serves as the Bank 2 VREF reference input."
},
{
"number": "47",
"name": "IP_L03P_2",
"type": "input",
"description": "Input-only true line of pair L03 in Bank 2, with no output structure."
},
{
"number": "57",
"name": "IP_L06N_2/M2/GCLK1",
"type": "input",
"description": "Input-only pin used as M2 mode select during configuration; avoid using GCLK1 as a clock because it is shared with the M2 function."
},
{
"number": "56",
"name": "IP_L06P_2/RDWR_B/GCLK0",
"type": "input",
"description": "Input-only RDWR_B pin that must be Low throughout parallel configuration; also global clock input GCLK0."
},
{
"number": "42",
"name": "VCCO_2",
"type": "power_in",
"description": "Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage."
},
{
"number": "49",
"name": "VCCO_2",
"type": "power_in",
"description": "Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage."
},
{
"number": "64",
"name": "VCCO_2",
"type": "power_in",
"description": "Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage."
},
{
"number": "31",
"name": "IP/VREF_3",
"type": "input",
"description": "Input-only VREF pin for Bank 3 on the XC3S100E (VREF(I/O) on the XC3S250E); if used for VREF, all VREF pins in the bank must be connected."
},
{
"number": "3",
"name": "IO_L01N_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the inverted (N) line of differential pair L01 in Bank 3."
},
{
"number": "2",
"name": "IO_L01P_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L01 in Bank 3."
},
{
"number": "5",
"name": "IO_L02N_3/VREF_3",
"type": "bidirectional",
"description": "User I/O that serves as a VREF reference input for Bank 3; if used for VREF, all VREF pins in the bank must be connected."
},
{
"number": "4",
"name": "IO_L02P_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L02 in Bank 3."
},
{
"number": "8",
"name": "IO_L03N_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the inverted (N) line of differential pair L03 in Bank 3."
},
{
"number": "7",
"name": "IO_L03P_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L03 in Bank 3."
},
{
"number": "15",
"name": "IO_L04N_3/LHCLK1",
"type": "bidirectional",
"description": "Left-half clock input LHCLK1 that can also be a user I/O (inverted line of pair L04, Bank 3)."
},
{
"number": "14",
"name": "IO_L04P_3/LHCLK0",
"type": "bidirectional",
"description": "Left-half clock input LHCLK0 that can also be a user I/O (true line of pair L04, Bank 3)."
},
{
"number": "17",
"name": "IO_L05N_3/LHCLK3/IRDY2",
"type": "bidirectional",
"description": "Left-half clock input LHCLK3 with the IRDY2 PCI function; can also be a user I/O (inverted line of pair L05, Bank 3)."
},
{
"number": "16",
"name": "IO_L05P_3/LHCLK2",
"type": "bidirectional",
"description": "Left-half clock input LHCLK2 that can also be a user I/O (true line of pair L05, Bank 3)."
},
{
"number": "21",
"name": "IO_L06N_3/LHCLK5",
"type": "bidirectional",
"description": "Left-half clock input LHCLK5 that can also be a user I/O (inverted line of pair L06, Bank 3)."
},
{
"number": "20",
"name": "IO_L06P_3/LHCLK4/TRDY2",
"type": "bidirectional",
"description": "Left-half clock input LHCLK4 with the TRDY2 PCI function; can also be a user I/O (true line of pair L06, Bank 3)."
},
{
"number": "23",
"name": "IO_L07N_3/LHCLK7",
"type": "bidirectional",
"description": "Left-half clock input LHCLK7 that can also be a user I/O (inverted line of pair L07, Bank 3)."
},
{
"number": "22",
"name": "IO_L07P_3/LHCLK6",
"type": "bidirectional",
"description": "Left-half clock input LHCLK6 that can also be a user I/O (true line of pair L07, Bank 3)."
},
{
"number": "26",
"name": "IO_L08N_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the inverted (N) line of differential pair L08 in Bank 3."
},
{
"number": "25",
"name": "IO_L08P_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L08 in Bank 3."
},
{
"number": "33",
"name": "IO_L09N_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the inverted (N) line of differential pair L09 in Bank 3."
},
{
"number": "32",
"name": "IO_L09P_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L09 in Bank 3."
},
{
"number": "35",
"name": "IO_L10N_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the inverted (N) line of differential pair L10 in Bank 3."
},
{
"number": "34",
"name": "IO_L10P_3",
"type": "bidirectional",
"description": "Unrestricted user I/O; the true (P) line of differential pair L10 in Bank 3."
},
{
"number": "6",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "10",
"name": "IO",
"type": "bidirectional",
"description": "Unrestricted user I/O on the XC3S100E; the XC3S250E uses this ball as an input-only pin (migration difference in Table 139)."
},
{
"number": "18",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "24",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "29",
"name": "IO",
"type": "bidirectional",
"description": "Unrestricted user I/O on the XC3S100E; the XC3S250E uses this ball as an input-only pin (migration difference in Table 139)."
},
{
"number": "36",
"name": "IP",
"type": "input",
"description": "Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
},
{
"number": "12",
"name": "IP/VREF_3",
"type": "input",
"description": "Input-only pin that serves as the VREF reference input for Bank 3 when a bank standard requires it."
},
{
"number": "13",
"name": "VCCO_3",
"type": "power_in",
"description": "Output-driver supply for Bank 3 (left edge); all VCCO_3 pins must be connected to the same voltage."
},
{
"number": "28",
"name": "VCCO_3",
"type": "power_in",
"description": "Output-driver supply for Bank 3 (left edge); all VCCO_3 pins must be connected to the same voltage."
},
{
"number": "11",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "19",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "27",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "37",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "46",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "55",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "61",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "73",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "90",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "99",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "118",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "127",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "133",
"name": "GND",
"type": "power_in",
"description": "Ground pin; all GND pins must be connected."
},
{
"number": "72",
"name": "DONE",
"type": "bidirectional",
"description": "Open-drain bidirectional configuration-done pin: low during configuration, goes high when configuration completes, and requires an external 330 Ω pull-up to 2.5V."
},
{
"number": "1",
"name": "PROG_B",
"type": "input",
"description": "Active-Low program input; asserting Low for 500 ns or longer restarts configuration, and an external 4.7 kΩ pull-up to 2.5V is recommended."
},
{
"number": "110",
"name": "TCK",
"type": "input",
"description": "Dedicated JTAG test clock input, powered by VCCAUX; not available as a user I/O."
},
{
"number": "144",
"name": "TDI",
"type": "input",
"description": "Dedicated JTAG test data input, powered by VCCAUX; not available as a user I/O."
},
{
"number": "109",
"name": "TDO",
"type": "output",
"description": "Dedicated JTAG test data output, powered by VCCAUX; not available as a user I/O."
},
{
"number": "108",
"name": "TMS",
"type": "input",
"description": "Dedicated JTAG mode-select input, powered by VCCAUX; not available as a user I/O."
},
{
"number": "30",
"name": "VCCAUX",
"type": "power_in",
"description": "Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V."
},
{
"number": "65",
"name": "VCCAUX",
"type": "power_in",
"description": "Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V."
},
{
"number": "102",
"name": "VCCAUX",
"type": "power_in",
"description": "Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V."
},
{
"number": "137",
"name": "VCCAUX",
"type": "power_in",
"description": "Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V."
},
{
"number": "9",
"name": "VCCINT",
"type": "power_in",
"description": "Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V."
},
{
"number": "45",
"name": "VCCINT",
"type": "power_in",
"description": "Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V."
},
{
"number": "80",
"name": "VCCINT",
"type": "power_in",
"description": "Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V."
},
{
"number": "115",
"name": "VCCINT",
"type": "power_in",
"description": "Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Package size mismatch: the requested hint is TQFP-144 (20x20), but the datasheet lists the TQ144/TQG; Pins whose function differs between XC3S100E and XC3S250E in the shared TQ144 footprint. Values show; Pin types are KiCad-class assignments made by this extraction from the datasheet's pin-type rules (T",
"104/144 pins cited to the wrong page (name found elsewhere): ['132:IO@p174', '124:IO/VREF_0@p174', '113:IO_L01N_0@p174', '112:IO_L01P_0@p174']"
],
"pages_sent": 94,
"cost_usd": 0.3488,
"at": "2026-10-20T23:19:25"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590225380184928256",
"pages": 227,
"sha256": "f8f455bdc7d9d54f",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 144,
"described": 144,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "xc3s100e-4tqg144i.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
22.0,
22.0,
1.1
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "04375074474c94e835558669f44d0989e234e983d3964161956a27bc675357d1",
"checked": "2026-10-20",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "xc3s100e-4tqg144i-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
22.0,
22.0,
1.1
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "7a6d6f127f1286d55c37f3b519868628aad3354c81a68d9935401cbf75b963c9",
"checked": "2026-10-20",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}