XC3S100E-4TQG144I

XILINX · Programmable Logic Device (CPLDs/FPGAs) · TQFP-144(20x20)

XC3S100E-4TQG144I from XILINX, in a TQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
132	IO	bidirectional	Unrestricted, general-purpose user I/O pin in Bank 0.
124	IO/VREF_0	bidirectional	User I/O that serves as a VREF reference input for HSTL/SSTL standards in Bank 0; if used for VREF, all VREF pins in the bank must be connected.
113	IO_L01N_0	bidirectional	Unrestricted user I/O; the inverted (N) line of differential pair L01 in Bank 0.
112	IO_L01P_0	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L01 in Bank 0.
117	IO_L02N_0	bidirectional	Unrestricted user I/O; the inverted (N) line of differential pair L02 in Bank 0.
116	IO_L02P_0	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L02 in Bank 0.
123	IO_L04N_0/GCLK5	bidirectional	Global clock input GCLK5 (inverted line of pair L04) that can optionally clock the whole device and can also be a user I/O.
122	IO_L04P_0/GCLK4	bidirectional	Global clock input GCLK4 (true line of pair L04) that can optionally clock the whole device and can also be a user I/O.
126	IO_L05N_0/GCLK7	bidirectional	Global clock input GCLK7 (inverted line of pair L05) that can optionally clock the whole device and can also be a user I/O.
125	IO_L05P_0/GCLK6	bidirectional	Global clock input GCLK6 (true line of pair L05) that can optionally clock the whole device and can also be a user I/O.
131	IO_L07N_0/GCLK11	bidirectional	Global clock input GCLK11 (inverted line of pair L07) that can optionally clock the whole device and can also be a user I/O.
130	IO_L07P_0/GCLK10	bidirectional	Global clock input GCLK10 (true line of pair L07) that can optionally clock the whole device and can also be a user I/O.
135	IO_L08N_0/VREF_0	bidirectional	User I/O that serves as a VREF reference input for HSTL/SSTL standards in Bank 0; if used for VREF, all VREF pins in the bank must be connected.
134	IO_L08P_0	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L08 in Bank 0.
140	IO_L09N_0	bidirectional	Unrestricted user I/O; the inverted (N) line of differential pair L09 in Bank 0.
139	IO_L09P_0	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L09 in Bank 0.
143	IO_L10N_0/HSWAP	bidirectional	Dual-purpose HSWAP pin: when Low during configuration it enables pull-up resistors on all I/O pins to their VCCO, and it must stay at a constant logic level throughout configuration.
142	IO_L10P_0	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L10 in Bank 0.
111	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
114	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
136	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
141	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
120	IP_L03N_0	input	Input-only inverted (N) line of differential pair L03 in Bank 0, with no output structure.
119	IP_L03P_0	input	Input-only true (P) line of differential pair L03 in Bank 0, with no output structure.
129	IP_L06N_0/GCLK9	input	Input-only global clock input GCLK9 (inverted line of pair L06) that optionally clocks the entire device.
128	IP_L06P_0/GCLK8	input	Input-only global clock input GCLK8 (true line of pair L06) that optionally clocks the entire device.
121	VCCO_0	power_in	Output-driver supply for Bank 0 (top edge); all VCCO_0 pins must be connected to the same voltage (3.3V, 2.5V, 1.8V, 1.5V or 1.2V).
138	VCCO_0	power_in	Output-driver supply for Bank 0 (top edge); all VCCO_0 pins must be connected to the same voltage (3.3V, 2.5V, 1.8V, 1.5V or 1.2V).
98	IO/A0	bidirectional	Dual-purpose address output A0 in BPI parallel Flash configuration mode; becomes a user I/O after configuration.
83	IO/VREF_1	bidirectional	User I/O that serves as a VREF reference input in Bank 1; if used for VREF, all VREF pins in the bank must be connected.
75	IO_L01N_1/A15	bidirectional	Dual-purpose address output A15 in BPI mode and user I/O after configuration; inverted line of differential pair L01 in Bank 1.
74	IO_L01P_1/A16	bidirectional	Dual-purpose address output A16 in BPI mode and user I/O after configuration; true line of differential pair L01 in Bank 1.
77	IO_L02N_1/A13	bidirectional	Dual-purpose address output A13 in BPI mode and user I/O after configuration; inverted line of differential pair L02 in Bank 1.
76	IO_L02P_1/A14	bidirectional	Dual-purpose address output A14 in BPI mode and user I/O after configuration; true line of differential pair L02 in Bank 1.
82	IO_L03N_1/A11	bidirectional	Dual-purpose address output A11 in BPI mode and user I/O after configuration; inverted line of differential pair L03 in Bank 1.
81	IO_L03P_1/A12	bidirectional	Dual-purpose address output A12 in BPI mode and user I/O after configuration; true line of differential pair L03 in Bank 1.
86	IO_L04N_1/A9/RHCLK1	bidirectional	Right-half clock input RHCLK1 that also carries dual-purpose address output A9 in BPI mode; can be a user I/O.
85	IO_L04P_1/A10/RHCLK0	bidirectional	Right-half clock input RHCLK0 that also carries dual-purpose address output A10 in BPI mode; can be a user I/O.
88	IO_L05N_1/A7/RHCLK3/TRDY1	bidirectional	Right-half clock input RHCLK3 with dual-purpose address output A7 in BPI mode and the TRDY1 PCI function; can be a user I/O.
87	IO_L05P_1/A8/RHCLK2	bidirectional	Right-half clock input RHCLK2 that also carries dual-purpose address output A8 in BPI mode; can be a user I/O.
92	IO_L06N_1/A5/RHCLK5	bidirectional	Right-half clock input RHCLK5 that also carries dual-purpose address output A5 in BPI mode; can be a user I/O.
91	IO_L06P_1/A6/RHCLK4/IRDY1	bidirectional	Right-half clock input RHCLK4 with dual-purpose address output A6 in BPI mode and the IRDY1 PCI function; can be a user I/O.
94	IO_L07N_1/A3/RHCLK7	bidirectional	Right-half clock input RHCLK7 that also carries dual-purpose address output A3 in BPI mode; can be a user I/O.
93	IO_L07P_1/A4/RHCLK6	bidirectional	Right-half clock input RHCLK6 that also carries dual-purpose address output A4 in BPI mode; can be a user I/O.
97	IO_L08N_1/A1	bidirectional	Dual-purpose address output A1 in BPI mode and user I/O after configuration; inverted line of differential pair L08 in Bank 1.
96	IO_L08P_1/A2	bidirectional	Dual-purpose address output A2 in BPI mode and user I/O after configuration; true line of differential pair L08 in Bank 1.
104	IO_L09N_1/LDC0	bidirectional	Dual-purpose LDC0, the BPI PROM chip-select (CE#) output driven Low during configuration; user I/O after configuration.
103	IO_L09P_1/HDC	bidirectional	Dual-purpose HDC, the BPI PROM write-enable (WE#) output driven High throughout configuration; user I/O after configuration.
106	IO_L10N_1/LDC2	bidirectional	Dual-purpose LDC2, the BPI PROM byte-mode (BYTE#) control driven Low during configuration; user I/O after configuration.
105	IO_L10P_1/LDC1	bidirectional	Dual-purpose LDC1, the BPI PROM output-enable (OE#) control driven Low during configuration; user I/O after configuration.
78	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
84	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
89	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
101	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
107	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
95	IP/VREF_1	input	Input-only pin that serves as the VREF reference input for Bank 1 when a bank standard requires it.
79	VCCO_1	power_in	Output-driver supply for Bank 1 (right edge); all VCCO_1 pins must be connected to the same voltage.
100	VCCO_1	power_in	Output-driver supply for Bank 1 (right edge); all VCCO_1 pins must be connected to the same voltage.
52	IO/D5	bidirectional	Dual-purpose D5 data input for byte-wide parallel configuration; becomes a user I/O after configuration.
60	IO/M1	bidirectional	Dual-purpose M1 configuration mode-select pin, sampled when INIT_B goes High; becomes a user I/O after configuration.
66	IP/VREF_2	input	Input-only VREF pin for Bank 2 on the XC3S100E (VREF(I/O) on the XC3S250E); if used for VREF, all VREF pins in the bank must be connected.
40	IO_L01N_2/INIT_B	bidirectional	Open-drain INIT_B initialization indicator, active Low; requires an external 4.7 kΩ pull-up to VCCO_2 in daisy-chain applications, and becomes a user I/O after configuration.
39	IO_L01P_2/CSO_B	bidirectional	Chip-select output CSO_B, active Low, used in SPI and BPI configuration modes; becomes a user I/O after configuration.
44	IO_L02N_2/MOSI/CSI_B	bidirectional	Dual-purpose MOSI serial data output in SPI mode or CSI_B chip-select input in parallel modes (must be Low throughout configuration).
43	IO_L02P_2/DOUT/BUSY	bidirectional	Dual-purpose DOUT serial data output for daisy-chains or BUSY in parallel modes; BUSY must be monitored when CCLK exceeds 50 MHz.
51	IO_L04N_2/D6/GCLK13	bidirectional	Dual-purpose D6 data input in parallel configuration modes and global clock input GCLK13; can be a user I/O.
50	IO_L04P_2/D7/GCLK12	bidirectional	Dual-purpose D7 data input in parallel configuration modes and global clock input GCLK12; can be a user I/O.
54	IO_L05N_2/D3/GCLK15	bidirectional	Dual-purpose D3 data input in parallel configuration modes and global clock input GCLK15; can be a user I/O.
53	IO_L05P_2/D4/GCLK14	bidirectional	Dual-purpose D4 data input in parallel configuration modes and global clock input GCLK14; can be a user I/O.
59	IO_L07N_2/D1/GCLK3	bidirectional	Dual-purpose D1 data input in parallel configuration modes and global clock input GCLK3; can be a user I/O.
58	IO_L07P_2/D2/GCLK2	bidirectional	Dual-purpose D2 data input in parallel configuration modes and global clock input GCLK2; can be a user I/O.
63	IO_L08N_2/DIN/D0	bidirectional	Dual-purpose serial data input DIN in serial modes or D0 parallel data input; becomes a user I/O after configuration.
62	IO_L08P_2/M0	bidirectional	Dual-purpose M0 mode-select pin, sampled when INIT_B goes High; becomes a user I/O after configuration.
68	IO_L09N_2/VS1/A18	bidirectional	Dual-purpose VS1 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A18 in BPI mode.
67	IO_L09P_2/VS2/A19	bidirectional	Dual-purpose VS2 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A19 in BPI mode.
71	IO_L10N_2/CCLK	bidirectional	Dual-purpose configuration clock: FPGA-generated in master modes and an external clock input in slave modes; becomes a user I/O after configuration.
70	IO_L10P_2/VS0/A17	bidirectional	Dual-purpose VS0 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A17 in BPI mode.
38	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
41	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
69	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
48	IP_L03N_2/VREF_2	input	Input-only inverted line of pair L03 in Bank 2 that also serves as the Bank 2 VREF reference input.
47	IP_L03P_2	input	Input-only true line of pair L03 in Bank 2, with no output structure.
57	IP_L06N_2/M2/GCLK1	input	Input-only pin used as M2 mode select during configuration; avoid using GCLK1 as a clock because it is shared with the M2 function.
56	IP_L06P_2/RDWR_B/GCLK0	input	Input-only RDWR_B pin that must be Low throughout parallel configuration; also global clock input GCLK0.
42	VCCO_2	power_in	Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage.
49	VCCO_2	power_in	Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage.
64	VCCO_2	power_in	Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage.
31	IP/VREF_3	input	Input-only VREF pin for Bank 3 on the XC3S100E (VREF(I/O) on the XC3S250E); if used for VREF, all VREF pins in the bank must be connected.
3	IO_L01N_3	bidirectional	Unrestricted user I/O; the inverted (N) line of differential pair L01 in Bank 3.
2	IO_L01P_3	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L01 in Bank 3.
5	IO_L02N_3/VREF_3	bidirectional	User I/O that serves as a VREF reference input for Bank 3; if used for VREF, all VREF pins in the bank must be connected.
4	IO_L02P_3	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L02 in Bank 3.
8	IO_L03N_3	bidirectional	Unrestricted user I/O; the inverted (N) line of differential pair L03 in Bank 3.
7	IO_L03P_3	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L03 in Bank 3.
15	IO_L04N_3/LHCLK1	bidirectional	Left-half clock input LHCLK1 that can also be a user I/O (inverted line of pair L04, Bank 3).
14	IO_L04P_3/LHCLK0	bidirectional	Left-half clock input LHCLK0 that can also be a user I/O (true line of pair L04, Bank 3).
17	IO_L05N_3/LHCLK3/IRDY2	bidirectional	Left-half clock input LHCLK3 with the IRDY2 PCI function; can also be a user I/O (inverted line of pair L05, Bank 3).
16	IO_L05P_3/LHCLK2	bidirectional	Left-half clock input LHCLK2 that can also be a user I/O (true line of pair L05, Bank 3).
21	IO_L06N_3/LHCLK5	bidirectional	Left-half clock input LHCLK5 that can also be a user I/O (inverted line of pair L06, Bank 3).
20	IO_L06P_3/LHCLK4/TRDY2	bidirectional	Left-half clock input LHCLK4 with the TRDY2 PCI function; can also be a user I/O (true line of pair L06, Bank 3).
23	IO_L07N_3/LHCLK7	bidirectional	Left-half clock input LHCLK7 that can also be a user I/O (inverted line of pair L07, Bank 3).
22	IO_L07P_3/LHCLK6	bidirectional	Left-half clock input LHCLK6 that can also be a user I/O (true line of pair L07, Bank 3).
26	IO_L08N_3	bidirectional	Unrestricted user I/O; the inverted (N) line of differential pair L08 in Bank 3.
25	IO_L08P_3	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L08 in Bank 3.
33	IO_L09N_3	bidirectional	Unrestricted user I/O; the inverted (N) line of differential pair L09 in Bank 3.
32	IO_L09P_3	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L09 in Bank 3.
35	IO_L10N_3	bidirectional	Unrestricted user I/O; the inverted (N) line of differential pair L10 in Bank 3.
34	IO_L10P_3	bidirectional	Unrestricted user I/O; the true (P) line of differential pair L10 in Bank 3.
6	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
10	IO	bidirectional	Unrestricted user I/O on the XC3S100E; the XC3S250E uses this ball as an input-only pin (migration difference in Table 139).
18	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
24	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
29	IO	bidirectional	Unrestricted user I/O on the XC3S100E; the XC3S250E uses this ball as an input-only pin (migration difference in Table 139).
36	IP	input	Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
12	IP/VREF_3	input	Input-only pin that serves as the VREF reference input for Bank 3 when a bank standard requires it.
13	VCCO_3	power_in	Output-driver supply for Bank 3 (left edge); all VCCO_3 pins must be connected to the same voltage.
28	VCCO_3	power_in	Output-driver supply for Bank 3 (left edge); all VCCO_3 pins must be connected to the same voltage.
11	GND	power_in	Ground pin; all GND pins must be connected.
19	GND	power_in	Ground pin; all GND pins must be connected.
27	GND	power_in	Ground pin; all GND pins must be connected.
37	GND	power_in	Ground pin; all GND pins must be connected.
46	GND	power_in	Ground pin; all GND pins must be connected.
55	GND	power_in	Ground pin; all GND pins must be connected.
61	GND	power_in	Ground pin; all GND pins must be connected.
73	GND	power_in	Ground pin; all GND pins must be connected.
90	GND	power_in	Ground pin; all GND pins must be connected.
99	GND	power_in	Ground pin; all GND pins must be connected.
118	GND	power_in	Ground pin; all GND pins must be connected.
127	GND	power_in	Ground pin; all GND pins must be connected.
133	GND	power_in	Ground pin; all GND pins must be connected.
72	DONE	bidirectional	Open-drain bidirectional configuration-done pin: low during configuration, goes high when configuration completes, and requires an external 330 Ω pull-up to 2.5V.
1	PROG_B	input	Active-Low program input; asserting Low for 500 ns or longer restarts configuration, and an external 4.7 kΩ pull-up to 2.5V is recommended.
110	TCK	input	Dedicated JTAG test clock input, powered by VCCAUX; not available as a user I/O.
144	TDI	input	Dedicated JTAG test data input, powered by VCCAUX; not available as a user I/O.
109	TDO	output	Dedicated JTAG test data output, powered by VCCAUX; not available as a user I/O.
108	TMS	input	Dedicated JTAG mode-select input, powered by VCCAUX; not available as a user I/O.
30	VCCAUX	power_in	Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V.
65	VCCAUX	power_in	Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V.
102	VCCAUX	power_in	Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V.
137	VCCAUX	power_in	Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V.
9	VCCINT	power_in	Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V.
45	VCCINT	power_in	Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V.
80	VCCINT	power_in	Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V.
115	VCCINT	power_in	Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V.

Key specifications

Parameter	Value
Manufacturer	XILINX
Package	TQFP-144(20x20)
Category	Embedded Processors & Controllers
Pins	144

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	Dedicated pins(6) -0.5, VCCAUX + 0.5 V TIN Input signal transition time(7), - 500 ns	117

CAD (KiCad official)

Symbol: XC3S100E-4TQG144I
Footprint: Package_QFP:TQFP-144_20x20mm_P0.5mm
3D model: TQFP-144(20x20) (KiCad packages3D, STEP)
3D model files: xc3s100e-4tqg144i-etched.step / xc3s100e-4tqg144i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xc3s100e-4tqg144i.step / xc3s100e-4tqg144i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XILINX datasheet (227 pp, sha256 f8f455bdc7d9d54f, retrieved 2026-10-20, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# XC3S100E-4TQG144I

**XILINX** · Programmable Logic Device (CPLDs/FPGAs) · TQFP-144(20x20)

XC3S100E-4TQG144I from XILINX, in a TQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 132 | IO | bidirectional | Unrestricted, general-purpose user I/O pin in Bank 0. |
| 124 | IO/VREF_0 | bidirectional | User I/O that serves as a VREF reference input for HSTL/SSTL standards in Bank 0; if used for VREF, all VREF pins in the bank must be connected. |
| 113 | IO_L01N_0 | bidirectional | Unrestricted user I/O; the inverted (N) line of differential pair L01 in Bank 0. |
| 112 | IO_L01P_0 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L01 in Bank 0. |
| 117 | IO_L02N_0 | bidirectional | Unrestricted user I/O; the inverted (N) line of differential pair L02 in Bank 0. |
| 116 | IO_L02P_0 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L02 in Bank 0. |
| 123 | IO_L04N_0/GCLK5 | bidirectional | Global clock input GCLK5 (inverted line of pair L04) that can optionally clock the whole device and can also be a user I/O. |
| 122 | IO_L04P_0/GCLK4 | bidirectional | Global clock input GCLK4 (true line of pair L04) that can optionally clock the whole device and can also be a user I/O. |
| 126 | IO_L05N_0/GCLK7 | bidirectional | Global clock input GCLK7 (inverted line of pair L05) that can optionally clock the whole device and can also be a user I/O. |
| 125 | IO_L05P_0/GCLK6 | bidirectional | Global clock input GCLK6 (true line of pair L05) that can optionally clock the whole device and can also be a user I/O. |
| 131 | IO_L07N_0/GCLK11 | bidirectional | Global clock input GCLK11 (inverted line of pair L07) that can optionally clock the whole device and can also be a user I/O. |
| 130 | IO_L07P_0/GCLK10 | bidirectional | Global clock input GCLK10 (true line of pair L07) that can optionally clock the whole device and can also be a user I/O. |
| 135 | IO_L08N_0/VREF_0 | bidirectional | User I/O that serves as a VREF reference input for HSTL/SSTL standards in Bank 0; if used for VREF, all VREF pins in the bank must be connected. |
| 134 | IO_L08P_0 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L08 in Bank 0. |
| 140 | IO_L09N_0 | bidirectional | Unrestricted user I/O; the inverted (N) line of differential pair L09 in Bank 0. |
| 139 | IO_L09P_0 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L09 in Bank 0. |
| 143 | IO_L10N_0/HSWAP | bidirectional | Dual-purpose HSWAP pin: when Low during configuration it enables pull-up resistors on all I/O pins to their VCCO, and it must stay at a constant logic level throughout configuration. |
| 142 | IO_L10P_0 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L10 in Bank 0. |
| 111 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 114 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 136 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 141 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 120 | IP_L03N_0 | input | Input-only inverted (N) line of differential pair L03 in Bank 0, with no output structure. |
| 119 | IP_L03P_0 | input | Input-only true (P) line of differential pair L03 in Bank 0, with no output structure. |
| 129 | IP_L06N_0/GCLK9 | input | Input-only global clock input GCLK9 (inverted line of pair L06) that optionally clocks the entire device. |
| 128 | IP_L06P_0/GCLK8 | input | Input-only global clock input GCLK8 (true line of pair L06) that optionally clocks the entire device. |
| 121 | VCCO_0 | power_in | Output-driver supply for Bank 0 (top edge); all VCCO_0 pins must be connected to the same voltage (3.3V, 2.5V, 1.8V, 1.5V or 1.2V). |
| 138 | VCCO_0 | power_in | Output-driver supply for Bank 0 (top edge); all VCCO_0 pins must be connected to the same voltage (3.3V, 2.5V, 1.8V, 1.5V or 1.2V). |
| 98 | IO/A0 | bidirectional | Dual-purpose address output A0 in BPI parallel Flash configuration mode; becomes a user I/O after configuration. |
| 83 | IO/VREF_1 | bidirectional | User I/O that serves as a VREF reference input in Bank 1; if used for VREF, all VREF pins in the bank must be connected. |
| 75 | IO_L01N_1/A15 | bidirectional | Dual-purpose address output A15 in BPI mode and user I/O after configuration; inverted line of differential pair L01 in Bank 1. |
| 74 | IO_L01P_1/A16 | bidirectional | Dual-purpose address output A16 in BPI mode and user I/O after configuration; true line of differential pair L01 in Bank 1. |
| 77 | IO_L02N_1/A13 | bidirectional | Dual-purpose address output A13 in BPI mode and user I/O after configuration; inverted line of differential pair L02 in Bank 1. |
| 76 | IO_L02P_1/A14 | bidirectional | Dual-purpose address output A14 in BPI mode and user I/O after configuration; true line of differential pair L02 in Bank 1. |
| 82 | IO_L03N_1/A11 | bidirectional | Dual-purpose address output A11 in BPI mode and user I/O after configuration; inverted line of differential pair L03 in Bank 1. |
| 81 | IO_L03P_1/A12 | bidirectional | Dual-purpose address output A12 in BPI mode and user I/O after configuration; true line of differential pair L03 in Bank 1. |
| 86 | IO_L04N_1/A9/RHCLK1 | bidirectional | Right-half clock input RHCLK1 that also carries dual-purpose address output A9 in BPI mode; can be a user I/O. |
| 85 | IO_L04P_1/A10/RHCLK0 | bidirectional | Right-half clock input RHCLK0 that also carries dual-purpose address output A10 in BPI mode; can be a user I/O. |
| 88 | IO_L05N_1/A7/RHCLK3/TRDY1 | bidirectional | Right-half clock input RHCLK3 with dual-purpose address output A7 in BPI mode and the TRDY1 PCI function; can be a user I/O. |
| 87 | IO_L05P_1/A8/RHCLK2 | bidirectional | Right-half clock input RHCLK2 that also carries dual-purpose address output A8 in BPI mode; can be a user I/O. |
| 92 | IO_L06N_1/A5/RHCLK5 | bidirectional | Right-half clock input RHCLK5 that also carries dual-purpose address output A5 in BPI mode; can be a user I/O. |
| 91 | IO_L06P_1/A6/RHCLK4/IRDY1 | bidirectional | Right-half clock input RHCLK4 with dual-purpose address output A6 in BPI mode and the IRDY1 PCI function; can be a user I/O. |
| 94 | IO_L07N_1/A3/RHCLK7 | bidirectional | Right-half clock input RHCLK7 that also carries dual-purpose address output A3 in BPI mode; can be a user I/O. |
| 93 | IO_L07P_1/A4/RHCLK6 | bidirectional | Right-half clock input RHCLK6 that also carries dual-purpose address output A4 in BPI mode; can be a user I/O. |
| 97 | IO_L08N_1/A1 | bidirectional | Dual-purpose address output A1 in BPI mode and user I/O after configuration; inverted line of differential pair L08 in Bank 1. |
| 96 | IO_L08P_1/A2 | bidirectional | Dual-purpose address output A2 in BPI mode and user I/O after configuration; true line of differential pair L08 in Bank 1. |
| 104 | IO_L09N_1/LDC0 | bidirectional | Dual-purpose LDC0, the BPI PROM chip-select (CE#) output driven Low during configuration; user I/O after configuration. |
| 103 | IO_L09P_1/HDC | bidirectional | Dual-purpose HDC, the BPI PROM write-enable (WE#) output driven High throughout configuration; user I/O after configuration. |
| 106 | IO_L10N_1/LDC2 | bidirectional | Dual-purpose LDC2, the BPI PROM byte-mode (BYTE#) control driven Low during configuration; user I/O after configuration. |
| 105 | IO_L10P_1/LDC1 | bidirectional | Dual-purpose LDC1, the BPI PROM output-enable (OE#) control driven Low during configuration; user I/O after configuration. |
| 78 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 84 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 89 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 101 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 107 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 95 | IP/VREF_1 | input | Input-only pin that serves as the VREF reference input for Bank 1 when a bank standard requires it. |
| 79 | VCCO_1 | power_in | Output-driver supply for Bank 1 (right edge); all VCCO_1 pins must be connected to the same voltage. |
| 100 | VCCO_1 | power_in | Output-driver supply for Bank 1 (right edge); all VCCO_1 pins must be connected to the same voltage. |
| 52 | IO/D5 | bidirectional | Dual-purpose D5 data input for byte-wide parallel configuration; becomes a user I/O after configuration. |
| 60 | IO/M1 | bidirectional | Dual-purpose M1 configuration mode-select pin, sampled when INIT_B goes High; becomes a user I/O after configuration. |
| 66 | IP/VREF_2 | input | Input-only VREF pin for Bank 2 on the XC3S100E (VREF(I/O) on the XC3S250E); if used for VREF, all VREF pins in the bank must be connected. |
| 40 | IO_L01N_2/INIT_B | bidirectional | Open-drain INIT_B initialization indicator, active Low; requires an external 4.7 kΩ pull-up to VCCO_2 in daisy-chain applications, and becomes a user I/O after configuration. |
| 39 | IO_L01P_2/CSO_B | bidirectional | Chip-select output CSO_B, active Low, used in SPI and BPI configuration modes; becomes a user I/O after configuration. |
| 44 | IO_L02N_2/MOSI/CSI_B | bidirectional | Dual-purpose MOSI serial data output in SPI mode or CSI_B chip-select input in parallel modes (must be Low throughout configuration). |
| 43 | IO_L02P_2/DOUT/BUSY | bidirectional | Dual-purpose DOUT serial data output for daisy-chains or BUSY in parallel modes; BUSY must be monitored when CCLK exceeds 50 MHz. |
| 51 | IO_L04N_2/D6/GCLK13 | bidirectional | Dual-purpose D6 data input in parallel configuration modes and global clock input GCLK13; can be a user I/O. |
| 50 | IO_L04P_2/D7/GCLK12 | bidirectional | Dual-purpose D7 data input in parallel configuration modes and global clock input GCLK12; can be a user I/O. |
| 54 | IO_L05N_2/D3/GCLK15 | bidirectional | Dual-purpose D3 data input in parallel configuration modes and global clock input GCLK15; can be a user I/O. |
| 53 | IO_L05P_2/D4/GCLK14 | bidirectional | Dual-purpose D4 data input in parallel configuration modes and global clock input GCLK14; can be a user I/O. |
| 59 | IO_L07N_2/D1/GCLK3 | bidirectional | Dual-purpose D1 data input in parallel configuration modes and global clock input GCLK3; can be a user I/O. |
| 58 | IO_L07P_2/D2/GCLK2 | bidirectional | Dual-purpose D2 data input in parallel configuration modes and global clock input GCLK2; can be a user I/O. |
| 63 | IO_L08N_2/DIN/D0 | bidirectional | Dual-purpose serial data input DIN in serial modes or D0 parallel data input; becomes a user I/O after configuration. |
| 62 | IO_L08P_2/M0 | bidirectional | Dual-purpose M0 mode-select pin, sampled when INIT_B goes High; becomes a user I/O after configuration. |
| 68 | IO_L09N_2/VS1/A18 | bidirectional | Dual-purpose VS1 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A18 in BPI mode. |
| 67 | IO_L09P_2/VS2/A19 | bidirectional | Dual-purpose VS2 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A19 in BPI mode. |
| 71 | IO_L10N_2/CCLK | bidirectional | Dual-purpose configuration clock: FPGA-generated in master modes and an external clock input in slave modes; becomes a user I/O after configuration. |
| 70 | IO_L10P_2/VS0/A17 | bidirectional | Dual-purpose VS0 variant-select input in SPI mode (sampled when INIT_B goes High) or address output A17 in BPI mode. |
| 38 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 41 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 69 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 48 | IP_L03N_2/VREF_2 | input | Input-only inverted line of pair L03 in Bank 2 that also serves as the Bank 2 VREF reference input. |
| 47 | IP_L03P_2 | input | Input-only true line of pair L03 in Bank 2, with no output structure. |
| 57 | IP_L06N_2/M2/GCLK1 | input | Input-only pin used as M2 mode select during configuration; avoid using GCLK1 as a clock because it is shared with the M2 function. |
| 56 | IP_L06P_2/RDWR_B/GCLK0 | input | Input-only RDWR_B pin that must be Low throughout parallel configuration; also global clock input GCLK0. |
| 42 | VCCO_2 | power_in | Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage. |
| 49 | VCCO_2 | power_in | Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage. |
| 64 | VCCO_2 | power_in | Output-driver supply for Bank 2 (bottom edge), which connects to the configuration-source voltage; all VCCO_2 pins must be connected to the same voltage. |
| 31 | IP/VREF_3 | input | Input-only VREF pin for Bank 3 on the XC3S100E (VREF(I/O) on the XC3S250E); if used for VREF, all VREF pins in the bank must be connected. |
| 3 | IO_L01N_3 | bidirectional | Unrestricted user I/O; the inverted (N) line of differential pair L01 in Bank 3. |
| 2 | IO_L01P_3 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L01 in Bank 3. |
| 5 | IO_L02N_3/VREF_3 | bidirectional | User I/O that serves as a VREF reference input for Bank 3; if used for VREF, all VREF pins in the bank must be connected. |
| 4 | IO_L02P_3 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L02 in Bank 3. |
| 8 | IO_L03N_3 | bidirectional | Unrestricted user I/O; the inverted (N) line of differential pair L03 in Bank 3. |
| 7 | IO_L03P_3 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L03 in Bank 3. |
| 15 | IO_L04N_3/LHCLK1 | bidirectional | Left-half clock input LHCLK1 that can also be a user I/O (inverted line of pair L04, Bank 3). |
| 14 | IO_L04P_3/LHCLK0 | bidirectional | Left-half clock input LHCLK0 that can also be a user I/O (true line of pair L04, Bank 3). |
| 17 | IO_L05N_3/LHCLK3/IRDY2 | bidirectional | Left-half clock input LHCLK3 with the IRDY2 PCI function; can also be a user I/O (inverted line of pair L05, Bank 3). |
| 16 | IO_L05P_3/LHCLK2 | bidirectional | Left-half clock input LHCLK2 that can also be a user I/O (true line of pair L05, Bank 3). |
| 21 | IO_L06N_3/LHCLK5 | bidirectional | Left-half clock input LHCLK5 that can also be a user I/O (inverted line of pair L06, Bank 3). |
| 20 | IO_L06P_3/LHCLK4/TRDY2 | bidirectional | Left-half clock input LHCLK4 with the TRDY2 PCI function; can also be a user I/O (true line of pair L06, Bank 3). |
| 23 | IO_L07N_3/LHCLK7 | bidirectional | Left-half clock input LHCLK7 that can also be a user I/O (inverted line of pair L07, Bank 3). |
| 22 | IO_L07P_3/LHCLK6 | bidirectional | Left-half clock input LHCLK6 that can also be a user I/O (true line of pair L07, Bank 3). |
| 26 | IO_L08N_3 | bidirectional | Unrestricted user I/O; the inverted (N) line of differential pair L08 in Bank 3. |
| 25 | IO_L08P_3 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L08 in Bank 3. |
| 33 | IO_L09N_3 | bidirectional | Unrestricted user I/O; the inverted (N) line of differential pair L09 in Bank 3. |
| 32 | IO_L09P_3 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L09 in Bank 3. |
| 35 | IO_L10N_3 | bidirectional | Unrestricted user I/O; the inverted (N) line of differential pair L10 in Bank 3. |
| 34 | IO_L10P_3 | bidirectional | Unrestricted user I/O; the true (P) line of differential pair L10 in Bank 3. |
| 6 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 10 | IO | bidirectional | Unrestricted user I/O on the XC3S100E; the XC3S250E uses this ball as an input-only pin (migration difference in Table 139). |
| 18 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 24 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 29 | IO | bidirectional | Unrestricted user I/O on the XC3S100E; the XC3S250E uses this ball as an input-only pin (migration difference in Table 139). |
| 36 | IP | input | Unrestricted, general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode. |
| 12 | IP/VREF_3 | input | Input-only pin that serves as the VREF reference input for Bank 3 when a bank standard requires it. |
| 13 | VCCO_3 | power_in | Output-driver supply for Bank 3 (left edge); all VCCO_3 pins must be connected to the same voltage. |
| 28 | VCCO_3 | power_in | Output-driver supply for Bank 3 (left edge); all VCCO_3 pins must be connected to the same voltage. |
| 11 | GND | power_in | Ground pin; all GND pins must be connected. |
| 19 | GND | power_in | Ground pin; all GND pins must be connected. |
| 27 | GND | power_in | Ground pin; all GND pins must be connected. |
| 37 | GND | power_in | Ground pin; all GND pins must be connected. |
| 46 | GND | power_in | Ground pin; all GND pins must be connected. |
| 55 | GND | power_in | Ground pin; all GND pins must be connected. |
| 61 | GND | power_in | Ground pin; all GND pins must be connected. |
| 73 | GND | power_in | Ground pin; all GND pins must be connected. |
| 90 | GND | power_in | Ground pin; all GND pins must be connected. |
| 99 | GND | power_in | Ground pin; all GND pins must be connected. |
| 118 | GND | power_in | Ground pin; all GND pins must be connected. |
| 127 | GND | power_in | Ground pin; all GND pins must be connected. |
| 133 | GND | power_in | Ground pin; all GND pins must be connected. |
| 72 | DONE | bidirectional | Open-drain bidirectional configuration-done pin: low during configuration, goes high when configuration completes, and requires an external 330 Ω pull-up to 2.5V. |
| 1 | PROG_B | input | Active-Low program input; asserting Low for 500 ns or longer restarts configuration, and an external 4.7 kΩ pull-up to 2.5V is recommended. |
| 110 | TCK | input | Dedicated JTAG test clock input, powered by VCCAUX; not available as a user I/O. |
| 144 | TDI | input | Dedicated JTAG test data input, powered by VCCAUX; not available as a user I/O. |
| 109 | TDO | output | Dedicated JTAG test data output, powered by VCCAUX; not available as a user I/O. |
| 108 | TMS | input | Dedicated JTAG mode-select input, powered by VCCAUX; not available as a user I/O. |
| 30 | VCCAUX | power_in | Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V. |
| 65 | VCCAUX | power_in | Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V. |
| 102 | VCCAUX | power_in | Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V. |
| 137 | VCCAUX | power_in | Auxiliary supply, +2.5V; all VCCAUX pins must be connected to +2.5V. |
| 9 | VCCINT | power_in | Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V. |
| 45 | VCCINT | power_in | Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V. |
| 80 | VCCINT | power_in | Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V. |
| 115 | VCCINT | power_in | Internal core supply, +1.2V; all VCCINT pins must be connected to +1.2V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | XILINX |
| Package | TQFP-144(20x20) |
| Category | Embedded Processors & Controllers |
| Pins | 144 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | Dedicated pins(6) -0.5, VCCAUX + 0.5 V TIN Input signal transition time(7), - 500 ns | 117 |

## CAD (KiCad official)

- Symbol: `XC3S100E-4TQG144I`
- Footprint: `Package_QFP:TQFP-144_20x20mm_P0.5mm`
- 3D model: TQFP-144(20x20) (KiCad packages3D, STEP)
- 3D model files: `xc3s100e-4tqg144i-etched.step` / `xc3s100e-4tqg144i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xc3s100e-4tqg144i.step` / `xc3s100e-4tqg144i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [XILINX datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590225380184928256) (227 pp, sha256 `f8f455bdc7d9d54f`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xc3s100e-4tqg144i-datasheet.pdf)