# XC101S101

**Si Change** · Analog To Digital Converters (ADC) · SOT-23-6

XC101S101 from Si Change, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VA | power_in | Single supply input (4 V to 5.25 V) that also serves as the ADC reference; VA must be kept at or above the maximum VIN signal to avoid saturating the top conversion code. |
| 2 | GND | power_in | Analog input signal ground; all analog and digital signals are referenced to this pin. |
| 3 | VIN | power_in | Analog signal input with a range of 0 V to VA. |
| 4 | SCLK | input | Serial clock input that directly controls the conversion and readout process; the 14th falling edge ends the conversion cycle. |
| 5 | SDATA | output | Serial data output that delivers the conversion result MSB first, after 3 leading zeros, as 10 data bits, and enters tri-state after the 14th SCLK falling edge. |
| 6 | CS | input | Active-low chip select; a falling edge with SCLK wakes the device and starts a conversion, and the device aborts if CS is raised before 10 SCLK cycles. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Si Change |
| Package | SOT-23-6 |
| Category | Data Acquisition |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (single supply) | VA | 4 |  | 5.25 | V | Single-supply operation, as stated for XC101S101 | 2 |
| Differential nonlinearity error (DNL) | DNL | -1 |  | 1 | LSB |  | 2 |
| Integral nonlinearity error (INL) | INL | -1 |  | 1 | LSB |  | 2 |
| Operating temperature range |  | -40 |  | 85 | ℃ |  | 1 |
| Sampling rate |  | 500 |  | 800 | KSPS | XC101S101 sampling rate range | 2 |
| Wait time after SDATA tri-state before CS is pulled low for next conversion |  | 1 |  |  | μS | Taken from timing narrative: after SDATA enters tri-state, before CS is pulled low again | 3 |

## CAD (KiCad official)

- Symbol: `XC101S101`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `xc101s101-etched.step` / `xc101s101-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `xc101s101.step` / `xc101s101.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Si Change datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603387432834785280) (4 pp, sha256 `4f37cb8551b3c94a`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/xc101s101-datasheet.pdf)