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WL9100S3-33B
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WPMtek Wei Pan Microelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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WL9100S3-33B
WPMtek Wei Pan Microelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L
WL9100S3-33B from WPMtek Wei Pan Microelectronics, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin; the datasheet asks for a wide, short copper trace from the input and output capacitor grounds back to this pin to limit parasitic inductance and resistance. |
| 2 | VOUT | power_out | Regulated output of the 3.3 V version (order code 33); output accuracy is ±2% and a ceramic output capacitor of at least 10 µF (X7R or X5R) must be placed as close as possible to VOUT and GND. |
| 3 | VIN | power_in | Power input with a recommended range of 3.0 V to 24 V and an absolute maximum of 40 V; a ceramic input capacitor of at least 1 µF should be placed as close as possible to VIN and GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WPMtek Wei Pan Microelectronics |
| Package | SOT-23-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 3 | 36 | V | 5 | ||
| Quiescent Current | IQ | 1.5 | 3 | µA | VIN = 12V, No Load | 5 | |
| Output Current | IOUT | 150 | mA | 5 | |||
| Dropout Voltage | VDROP | 450 | 550 | mV | IOUT = 100mA; VOUT = VOUTNOM, 0.1V | 5 | |
| Dropout Voltage | VDROP | 700 | 800 | mV | VOUT=3.3V, IOUT = 150mA; VOUT = VOUTNOM, 0.1V | 5 | |
| Load Regulation | ΔVLOAD | 0.03 | 0.05 | %/mA | VIN = VOUTNOM + 1V; 1mA ≤ IOUT ≤ 100mA | 5 | |
| Line Regulation | ΔVLINE | 0.01 | 0.02 | %/V | VOUTNOM + 1V ≤ VIN ≤ 24V; IOUT = 1mA | 5 | |
| Output voltage accuracy (grade B, default) | -2 | 2 | % | Ordering suffix B: ±2% (default) | 6 | ||
| Current Limit | ILIMIT | 200 | mA | 5 | |||
| Short Current | ISHORT | 90 | mA | 5 | |||
| Thermal Shutdown Temperature | TOTSD | 150 | °C | 5 | |||
| Thermal Shutdown Hysteresis | THYOTSD | 20 | °C | 5 | |||
| Output Noise Voltage | Von | 100 | µVrms | COUT = 10uF, IOUT = 30mA, BW = 10Hz~100kHz | 5 | ||
| Supply Input Voltage | VIN | -0.3 | 40 | V | 4 | ||
| VOUT to VIN | VOUT_VIN | -35 | -0.3 | V | 4 | ||
| Regulated Output Voltage | VOUT | -0.3 | 6 | V | 4 | ||
| Power Dissipation (SOT23-3) | PD | 450 | mW | @TA=+25℃ | 4 | ||
| Thermal Resistance, junction to air (SOT23-3) | θJA | 280 | °C /W | Junction to air | 4 | ||
| Human Body Model ESD | HBM | -4000 | 4000 | V | Human Body Model | 4 | |
| Charged Device Mode ESD | CDM | -2000 | 2000 | V | Charged Device Mode | 4 | |
| Machine Mode ESD | MM | 200 | V | Machine Mode | 4 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 4 | ||
| Operating Junction Temperature | TJ | 150 | °C | 4 | |||
| Lead Temperature | TLEAD | 260 | °C | Soldering 10s | 4 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 4 | ||
| Input Voltage | VIN | 3 | 24 | V | 4 | ||
| Output Voltage | VOUT | 1.8 | 5 | V | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | and output capacitors must be back to the WL9100 ground pin using as wide and as short of a copper trace as is practical.Connections using long trace lengths, narrow trace widths, and/or | 8 |
CAD (KiCad official)
- Symbol:
WL9100S3-33B - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3L (KiCad packages3D, STEP)
- 3D model files:
wl9100s3-33b-etched.step/wl9100s3-33b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);wl9100s3-33b.step/wl9100s3-33b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: WPMtek Wei Pan Microelectronics datasheet (8 pp, sha256
6437b9fd93db9e0e, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# WL9100S3-33B
**WPMtek Wei Pan Microelectronics** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L
WL9100S3-33B from WPMtek Wei Pan Microelectronics, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin; the datasheet asks for a wide, short copper trace from the input and output capacitor grounds back to this pin to limit parasitic inductance and resistance. |
| 2 | VOUT | power_out | Regulated output of the 3.3 V version (order code 33); output accuracy is ±2% and a ceramic output capacitor of at least 10 µF (X7R or X5R) must be placed as close as possible to VOUT and GND. |
| 3 | VIN | power_in | Power input with a recommended range of 3.0 V to 24 V and an absolute maximum of 40 V; a ceramic input capacitor of at least 1 µF should be placed as close as possible to VIN and GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WPMtek Wei Pan Microelectronics |
| Package | SOT-23-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 3 | | 36 | V | | 5 |
| Quiescent Current | IQ | | 1.5 | 3 | µA | VIN = 12V, No Load | 5 |
| Output Current | IOUT | 150 | | | mA | | 5 |
| Dropout Voltage | VDROP | | 450 | 550 | mV | IOUT = 100mA; VOUT = VOUTNOM, 0.1V | 5 |
| Dropout Voltage | VDROP | | 700 | 800 | mV | VOUT=3.3V, IOUT = 150mA; VOUT = VOUTNOM, 0.1V | 5 |
| Load Regulation | ΔVLOAD | | 0.03 | 0.05 | %/mA | VIN = VOUTNOM + 1V; 1mA ≤ IOUT ≤ 100mA | 5 |
| Line Regulation | ΔVLINE | | 0.01 | 0.02 | %/V | VOUTNOM + 1V ≤ VIN ≤ 24V; IOUT = 1mA | 5 |
| Output voltage accuracy (grade B, default) | | -2 | | 2 | % | Ordering suffix B: ±2% (default) | 6 |
| Current Limit | ILIMIT | | 200 | | mA | | 5 |
| Short Current | ISHORT | | 90 | | mA | | 5 |
| Thermal Shutdown Temperature | TOTSD | | 150 | | °C | | 5 |
| Thermal Shutdown Hysteresis | THYOTSD | | 20 | | °C | | 5 |
| Output Noise Voltage | Von | | 100 | | µVrms | COUT = 10uF, IOUT = 30mA, BW = 10Hz~100kHz | 5 |
| Supply Input Voltage | VIN | -0.3 | | 40 | V | | 4 |
| VOUT to VIN | VOUT_VIN | -35 | | -0.3 | V | | 4 |
| Regulated Output Voltage | VOUT | -0.3 | | 6 | V | | 4 |
| Power Dissipation (SOT23-3) | PD | | | 450 | mW | @TA=+25℃ | 4 |
| Thermal Resistance, junction to air (SOT23-3) | θJA | | 280 | | °C /W | Junction to air | 4 |
| Human Body Model ESD | HBM | -4000 | | 4000 | V | Human Body Model | 4 |
| Charged Device Mode ESD | CDM | -2000 | | 2000 | V | Charged Device Mode | 4 |
| Machine Mode ESD | MM | | | 200 | V | Machine Mode | 4 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 4 |
| Operating Junction Temperature | TJ | | | 150 | °C | | 4 |
| Lead Temperature | TLEAD | | | 260 | °C | Soldering 10s | 4 |
| Operating Ambient Temperature | TA | -40 | | 85 | °C | | 4 |
| Input Voltage | VIN | 3 | | 24 | V | | 4 |
| Output Voltage | VOUT | 1.8 | | 5 | V | | 4 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | and output capacitors must be back to the WL9100 ground pin using as wide and as short of a copper trace as is practical.Connections using long trace lengths, narrow trace widths, and/or | 8 |
## CAD (KiCad official)
- Symbol: `WL9100S3-33B`
- Footprint: `Package_TO_SOT_SMD:SOT-23-3`
- 3D model: SOT-23-3L (KiCad packages3D, STEP)
- 3D model files: `wl9100s3-33b-etched.step` / `wl9100s3-33b-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `wl9100s3-33b.step` / `wl9100s3-33b.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [WPMtek Wei Pan Microelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757102783235805184) (8 pp, sha256 `6437b9fd93db9e0e`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/wl9100s3-33b-datasheet.pdf)