component
WGI210AT S LJXR
Public Made by Adomby adom
Intel/Altera Others, QFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "wgi210at-s-ljxr",
"title": "WGI210AT S LJXR",
"brief": "Intel/Altera Others, QFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"others",
"wgi210at s ljxr",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "WGI210AT S LJXR",
"manufacturer": "Intel/Altera",
"package": "QFN-64(9x9)",
"pin_count": 65,
"category": "Others",
"subcategory": "Others",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/55920bb37ba695522d538e54694c34f4.pdf",
"parts": {
"symbol": "wgi210at-s-ljxr.kicad_sym",
"footprint": "wgi210at-s-ljxr.kicad_mod",
"model_3d": "wgi210at-s-ljxr-hero.glb",
"model_3d_plain": "wgi210at-s-ljxr-etched.glb",
"model_3d_step": "wgi210at-s-ljxr-etched.step",
"model_3d_step_plain": "wgi210at-s-ljxr.step",
"lbr": "wgi210at-s-ljxr.lbr"
},
"distributor_links": {
"lcsc": "C7433263",
"mouser": "607-WGI210ATSLJXR"
},
"distributor_check": {
"checked_at": "2026-10-23T03:19:00Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": "607-WGI210ATSLJXR",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "LAN_PWR_GOOD",
"type": "input",
"description": "LAN power-good input; no internal pull-up in any state, external pull-up is listed."
},
{
"number": "2",
"name": "NC_SI_CLK_IN",
"type": "input",
"description": "NC-SI reference clock input, high-impedance when active, external pull-down listed."
},
{
"number": "3",
"name": "NC_SI_CRS_DV",
"type": "output",
"description": "NC-SI carrier sense/receive data valid signal, high-impedance when active, external pull-down listed."
},
{
"number": "4",
"name": "JTAG_TDO",
"type": "output",
"description": "JTAG test data output, open-drain, to be connected to VCC33 through a 3.3 K pull-up."
},
{
"number": "5",
"name": "NC_SI_RXD1",
"type": "output",
"description": "NC-SI receive data bit 1, high-impedance when active, external pull-up listed."
},
{
"number": "6",
"name": "NC_SI_RXD0",
"type": "output",
"description": "NC-SI receive data bit 0, high-impedance when active, external pull-up listed."
},
{
"number": "7",
"name": "NC_SI_TX_EN",
"type": "input",
"description": "NC-SI transmit enable input, high-impedance when active, external pull-down listed."
},
{
"number": "8",
"name": "NC_SI_TXD1",
"type": "input",
"description": "NC-SI transmit data bit 1, high-impedance when active, external pull-up listed."
},
{
"number": "9",
"name": "NC_SI_TXD0",
"type": "input",
"description": "NC-SI transmit data bit 0, high-impedance when active, external pull-up listed."
},
{
"number": "10",
"name": "VDD3p3",
"type": "power_in",
"description": "3.3 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "11",
"name": "VDD0p9",
"type": "power_in",
"description": "0.9 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "12",
"name": "NVM_SI",
"type": "output",
"description": "Serial Flash (SPI) data input line to the Flash, with an internal pull-up (about 30 K) in the disable state."
},
{
"number": "13",
"name": "NVM_SK",
"type": "output",
"description": "Serial Flash (SPI) clock output, with internal pull-up in power-up and disable states."
},
{
"number": "14",
"name": "NVM_SO",
"type": "input",
"description": "Serial Flash (SPI) data output from the Flash, with internal pull-up in power-up, active and disable states."
},
{
"number": "15",
"name": "NVM_CS_N",
"type": "output",
"description": "Serial Flash (SPI) chip select, active low, with internal pull-up in power-up and disable states."
},
{
"number": "16",
"name": "PE_WAKE_N",
"type": "bidirectional",
"description": "PCIe wake signal that also carries OBFF; external pull-up listed."
},
{
"number": "17",
"name": "PE_RST_N",
"type": "input",
"description": "PCIe reset input, external pull-up listed."
},
{
"number": "18",
"name": "JTAG_TMS",
"type": "input",
"description": "JTAG test mode select, to be connected to VCC33 through a 3.3 K pull-up."
},
{
"number": "19",
"name": "JTAG_CLK",
"type": "input",
"description": "JTAG test clock input, to be connected to ground through a 3.3 K pull-down."
},
{
"number": "20",
"name": "PE_Tn",
"type": "output",
"description": "PCIe v2.1 (2.5 GT/s) x1 transmit differential pair, negative."
},
{
"number": "21",
"name": "PE_Tp",
"type": "output",
"description": "PCIe v2.1 (2.5 GT/s) x1 transmit differential pair, positive."
},
{
"number": "22",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "23",
"name": "PE_Rn",
"type": "input",
"description": "PCIe v2.1 (2.5 GT/s) x1 receive differential pair, negative."
},
{
"number": "24",
"name": "PE_Rp",
"type": "input",
"description": "PCIe v2.1 (2.5 GT/s) x1 receive differential pair, positive."
},
{
"number": "25",
"name": "PECLKn",
"type": "input",
"description": "PCIe reference clock differential input, negative."
},
{
"number": "26",
"name": "PECLKp",
"type": "input",
"description": "PCIe reference clock differential input, positive."
},
{
"number": "27",
"name": "VDD3p3",
"type": "power_in",
"description": "3.3 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "28",
"name": "DEV_OFF_N",
"type": "input",
"description": "Device-off control input (active low) used for the device disable function."
},
{
"number": "29",
"name": "JTAG_TDI",
"type": "input",
"description": "JTAG test data input, to be connected to VCC33 through a 3.3 K pull-up."
},
{
"number": "30",
"name": "LED1",
"type": "output",
"description": "LED driver output, also the XOR tree output in XOR test mode."
},
{
"number": "31",
"name": "LED0",
"type": "output",
"description": "Configurable LED driver output."
},
{
"number": "32",
"name": "VDD0p9",
"type": "power_in",
"description": "0.9 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "33",
"name": "LED2",
"type": "output",
"description": "Configurable LED driver output."
},
{
"number": "34",
"name": "SMB_CLK",
"type": "bidirectional",
"description": "SMBus clock; external pull-up listed."
},
{
"number": "35",
"name": "SMB_ALRT_N",
"type": "bidirectional",
"description": "SMBus alert, active low; external pull-up listed."
},
{
"number": "36",
"name": "SMB_DAT",
"type": "bidirectional",
"description": "SMBus data; external pull-up listed."
},
{
"number": "37",
"name": "CBOT",
"type": "passive",
"description": "Bottom capacitor connection for the integrated switching regulator (15 uF per Figure 12-22)."
},
{
"number": "38",
"name": "VDD0p9_OUT",
"type": "power_out",
"description": "Integrated 0.9 V switching regulator output, to be fed back to the VDD0p9 pins."
},
{
"number": "39",
"name": "VDD1p5_OUT",
"type": "power_out",
"description": "Integrated 1.5 V switching regulator output, to be fed back to the VDD1p5 pins."
},
{
"number": "40",
"name": "CTOP",
"type": "passive",
"description": "Top capacitor connection for the integrated switching regulator (15 uF per Figure 12-22)."
},
{
"number": "41",
"name": "VDD3p3",
"type": "power_in",
"description": "3.3 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "42",
"name": "VDD0p9",
"type": "power_in",
"description": "0.9 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "43",
"name": "NC_SI_ARB_IN",
"type": "input",
"description": "NC-SI hardware arbitration input, high-impedance when active."
},
{
"number": "44",
"name": "NC_SI_ARB_OUT",
"type": "output",
"description": "NC-SI hardware arbitration output, stable high output in power-up."
},
{
"number": "45",
"name": "XTAL2",
"type": "passive",
"description": "Crystal oscillator connection, output side."
},
{
"number": "46",
"name": "XTAL1",
"type": "input",
"description": "Crystal oscillator connection, input side or external clock input."
},
{
"number": "47",
"name": "VDD1p5",
"type": "power_in",
"description": "1.5 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "48",
"name": "RSET",
"type": "passive",
"description": "Analog bias reference resistor connection."
},
{
"number": "49",
"name": "MDI_MINUS[3]",
"type": "bidirectional",
"description": "Copper PHY MDI differential pair 3, negative."
},
{
"number": "50",
"name": "MDI_PLUS[3]",
"type": "bidirectional",
"description": "Copper PHY MDI differential pair 3, positive."
},
{
"number": "51",
"name": "VDD3p3",
"type": "power_in",
"description": "In BASE-T, 3.3 V analog power supply to the GPHY."
},
{
"number": "52",
"name": "MDI_MINUS[2]",
"type": "bidirectional",
"description": "Copper PHY MDI differential pair 2, negative."
},
{
"number": "53",
"name": "MDI_PLUS[2]",
"type": "bidirectional",
"description": "Copper PHY MDI differential pair 2, positive."
},
{
"number": "54",
"name": "MDI_MINUS[1]",
"type": "bidirectional",
"description": "Copper PHY MDI differential pair 1, negative."
},
{
"number": "55",
"name": "MDI_PLUS[1]",
"type": "bidirectional",
"description": "Copper PHY MDI differential pair 1, positive."
},
{
"number": "56",
"name": "VDD1p5",
"type": "power_in",
"description": "In BASE-T, 1.5 V analog power supply to the GPHY."
},
{
"number": "57",
"name": "MDI_MINUS[0]",
"type": "bidirectional",
"description": "Copper PHY MDI differential pair 0, negative."
},
{
"number": "58",
"name": "MDI_PLUS[0]",
"type": "bidirectional",
"description": "Copper PHY MDI differential pair 0, positive."
},
{
"number": "59",
"name": "VDD0p9",
"type": "power_in",
"description": "0.9 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "60",
"name": "SDP3",
"type": "bidirectional",
"description": "Software-definable pin 3, configurable as input, GPI input or output."
},
{
"number": "61",
"name": "SDP1",
"type": "bidirectional",
"description": "Software-definable pin 1 (also marked PCIe_DIS), with internal pull-up until Flash auto-load is done."
},
{
"number": "62",
"name": "SDP2",
"type": "bidirectional",
"description": "Software-definable pin 2, with internal pull-up until Flash auto-load is done; can carry I2C."
},
{
"number": "63",
"name": "SDP0",
"type": "bidirectional",
"description": "Software-definable pin 0, with internal pull-up until Flash auto-load is done; can carry I2C."
},
{
"number": "64",
"name": "VDD3p3",
"type": "power_in",
"description": "3.3 V supply pin, one decoupling capacitor per VDD pin recommended."
},
{
"number": "65",
"name": "E_PAD_GND",
"type": "power_in",
"description": "Exposed pad, which is ground."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The provided pages do not include the pin description tables (Section 2.3). Pin types and descriptio; The pin assignment figure is flattened text, so the Copper/SerDes column mapping for pins 49-58 was ; The exposed pad is not numbered in the figure. Number 65 is taken from the E_PAD_GND label in Figure",
"9/65 pins cited to the wrong page (name found elsewhere): ['18:JTAG_TMS@p845', '19:JTAG_CLK@p845', '29:JTAG_TDI@p845', '31:LED0@p11']"
],
"pages_sent": 30,
"cost_usd": 0.3897,
"at": "2026-10-23T03:18:44"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/55920bb37ba695522d538e54694c34f4.pdf",
"pages": 870,
"sha256": "f57605388f62a6a2",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 65,
"described": 65,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
},
"models_3d": [
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"file": "wgi210at-s-ljxr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
9,
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"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",
"checked": "2026-10-23",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "wgi210at-s-ljxr-etched.step",
"role": "eda",
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"seat": "z = 0",
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"zmin_mm": 0,
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"footprint_binding": "identity",
"sha256": "68b130ff1a32d75fa220ae79a2ff80a94df85913ef69492a86b5f709b5966fc8",
"checked": "2026-10-23",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Intel/Altera",
"Package": "QFN-64(9x9)",
"Category": "Others",
"Pins": "65"
},
"appearance": {
"contacts": {
"quote": "The I2C interface can alternatively be run over the SDP 0 and SDP2 pins. This can be useful when the I210 operates with a copper PHY since the dedicated SFPx_I2C pins are not available in this mode fo",
"page": 11,
"doc": "ds.pdf",
"material": "copper"
},
"housing": {
"quote": "0x4228 N/A SCVPC SerDes/SGMII/1000BASE-KX Code Violation Packet Count",
"page": 373,
"doc": "ds.pdf",
"material": "PC"
},
"version": 1,
"datasheet_sha256": "f57605388f62a6a2d010c20fab392f8e3c0cc6e618f030ea045bc85ff82ec9ee"
}
},
"variants": [],
"sections": [
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"breadcrumbs",
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],
"discovery_triggers": [
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],
"discovery_pitch": "WGI210AT S LJXR (Intel/Altera) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
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}