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WGI210AT S LJXR

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Intel/Altera Others, QFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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WGI210AT S LJXR

Intel/Altera · Others · QFN-64(9x9)

WGI210AT S LJXR from Intel/Altera, in a QFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LAN_PWR_GOOD input LAN power-good input; no internal pull-up in any state, external pull-up is listed.
2 NC_SI_CLK_IN input NC-SI reference clock input, high-impedance when active, external pull-down listed.
3 NC_SI_CRS_DV output NC-SI carrier sense/receive data valid signal, high-impedance when active, external pull-down listed.
4 JTAG_TDO output JTAG test data output, open-drain, to be connected to VCC33 through a 3.3 K pull-up.
5 NC_SI_RXD1 output NC-SI receive data bit 1, high-impedance when active, external pull-up listed.
6 NC_SI_RXD0 output NC-SI receive data bit 0, high-impedance when active, external pull-up listed.
7 NC_SI_TX_EN input NC-SI transmit enable input, high-impedance when active, external pull-down listed.
8 NC_SI_TXD1 input NC-SI transmit data bit 1, high-impedance when active, external pull-up listed.
9 NC_SI_TXD0 input NC-SI transmit data bit 0, high-impedance when active, external pull-up listed.
10 VDD3p3 power_in 3.3 V supply pin, one decoupling capacitor per VDD pin recommended.
11 VDD0p9 power_in 0.9 V supply pin, one decoupling capacitor per VDD pin recommended.
12 NVM_SI output Serial Flash (SPI) data input line to the Flash, with an internal pull-up (about 30 K) in the disable state.
13 NVM_SK output Serial Flash (SPI) clock output, with internal pull-up in power-up and disable states.
14 NVM_SO input Serial Flash (SPI) data output from the Flash, with internal pull-up in power-up, active and disable states.
15 NVM_CS_N output Serial Flash (SPI) chip select, active low, with internal pull-up in power-up and disable states.
16 PE_WAKE_N bidirectional PCIe wake signal that also carries OBFF; external pull-up listed.
17 PE_RST_N input PCIe reset input, external pull-up listed.
18 JTAG_TMS input JTAG test mode select, to be connected to VCC33 through a 3.3 K pull-up.
19 JTAG_CLK input JTAG test clock input, to be connected to ground through a 3.3 K pull-down.
20 PE_Tn output PCIe v2.1 (2.5 GT/s) x1 transmit differential pair, negative.
21 PE_Tp output PCIe v2.1 (2.5 GT/s) x1 transmit differential pair, positive.
22 NC unconnected No connect.
23 PE_Rn input PCIe v2.1 (2.5 GT/s) x1 receive differential pair, negative.
24 PE_Rp input PCIe v2.1 (2.5 GT/s) x1 receive differential pair, positive.
25 PECLKn input PCIe reference clock differential input, negative.
26 PECLKp input PCIe reference clock differential input, positive.
27 VDD3p3 power_in 3.3 V supply pin, one decoupling capacitor per VDD pin recommended.
28 DEV_OFF_N input Device-off control input (active low) used for the device disable function.
29 JTAG_TDI input JTAG test data input, to be connected to VCC33 through a 3.3 K pull-up.
30 LED1 output LED driver output, also the XOR tree output in XOR test mode.
31 LED0 output Configurable LED driver output.
32 VDD0p9 power_in 0.9 V supply pin, one decoupling capacitor per VDD pin recommended.
33 LED2 output Configurable LED driver output.
34 SMB_CLK bidirectional SMBus clock; external pull-up listed.
35 SMB_ALRT_N bidirectional SMBus alert, active low; external pull-up listed.
36 SMB_DAT bidirectional SMBus data; external pull-up listed.
37 CBOT passive Bottom capacitor connection for the integrated switching regulator (15 uF per Figure 12-22).
38 VDD0p9_OUT power_out Integrated 0.9 V switching regulator output, to be fed back to the VDD0p9 pins.
39 VDD1p5_OUT power_out Integrated 1.5 V switching regulator output, to be fed back to the VDD1p5 pins.
40 CTOP passive Top capacitor connection for the integrated switching regulator (15 uF per Figure 12-22).
41 VDD3p3 power_in 3.3 V supply pin, one decoupling capacitor per VDD pin recommended.
42 VDD0p9 power_in 0.9 V supply pin, one decoupling capacitor per VDD pin recommended.
43 NC_SI_ARB_IN input NC-SI hardware arbitration input, high-impedance when active.
44 NC_SI_ARB_OUT output NC-SI hardware arbitration output, stable high output in power-up.
45 XTAL2 passive Crystal oscillator connection, output side.
46 XTAL1 input Crystal oscillator connection, input side or external clock input.
47 VDD1p5 power_in 1.5 V supply pin, one decoupling capacitor per VDD pin recommended.
48 RSET passive Analog bias reference resistor connection.
49 MDI_MINUS[3] bidirectional Copper PHY MDI differential pair 3, negative.
50 MDI_PLUS[3] bidirectional Copper PHY MDI differential pair 3, positive.
51 VDD3p3 power_in In BASE-T, 3.3 V analog power supply to the GPHY.
52 MDI_MINUS[2] bidirectional Copper PHY MDI differential pair 2, negative.
53 MDI_PLUS[2] bidirectional Copper PHY MDI differential pair 2, positive.
54 MDI_MINUS[1] bidirectional Copper PHY MDI differential pair 1, negative.
55 MDI_PLUS[1] bidirectional Copper PHY MDI differential pair 1, positive.
56 VDD1p5 power_in In BASE-T, 1.5 V analog power supply to the GPHY.
57 MDI_MINUS[0] bidirectional Copper PHY MDI differential pair 0, negative.
58 MDI_PLUS[0] bidirectional Copper PHY MDI differential pair 0, positive.
59 VDD0p9 power_in 0.9 V supply pin, one decoupling capacitor per VDD pin recommended.
60 SDP3 bidirectional Software-definable pin 3, configurable as input, GPI input or output.
61 SDP1 bidirectional Software-definable pin 1 (also marked PCIe_DIS), with internal pull-up until Flash auto-load is done.
62 SDP2 bidirectional Software-definable pin 2, with internal pull-up until Flash auto-load is done; can carry I2C.
63 SDP0 bidirectional Software-definable pin 0, with internal pull-up until Flash auto-load is done; can carry I2C.
64 VDD3p3 power_in 3.3 V supply pin, one decoupling capacitor per VDD pin recommended.
65 E_PAD_GND power_in Exposed pad, which is ground.

Key specifications

Parameter Value
Manufacturer Intel/Altera
Package QFN-64(9x9)
Category Others
Pins 65

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 0x4228 N/A SCVPC SerDes/SGMII/1000BASE-KX Code Violation Packet Count 373
contacts copper The I2C interface can alternatively be run over the SDP 0 and SDP2 pins. This can be useful when the I210 operates with a copper PHY since the dedicated SFPx_I2C pins are not available in this mode fo 11

CAD (KiCad official)

  • Symbol: WGI210AT S LJXR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: wgi210at-s-ljxr-etched.step / wgi210at-s-ljxr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); wgi210at-s-ljxr.step / wgi210at-s-ljxr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Intel/Altera datasheet (870 pp, sha256 f57605388f62a6a2, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF