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W78E054DFG

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Nuvoton Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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W78E054DFG

Nuvoton Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-44(10x10)

W78E054DFG from Nuvoton Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.5 bidirectional Port 1 bit 5, bi-directional I/O with internal pull-up.
2 P1.6 bidirectional Port 1 bit 6, bi-directional I/O with internal pull-up.
3 P1.7 bidirectional Port 1 bit 7, bi-directional I/O with internal pull-up.
4 RST input Reset input: a high for two machine cycles while the oscillator is running resets the device; internal pull-down resistor 100-225 kOhm.
5 P3.0/RXD bidirectional Port 3 bit 0 with internal pull-up; alternate function is serial port 0 input RXD.
6 P4.3/INT2 bidirectional Port 4 bit 3 general I/O or external interrupt 2 input.
7 P3.1/TXD bidirectional Port 3 bit 1 with internal pull-up; alternate function is serial port 0 output TXD.
8 P3.2/INT0 bidirectional Port 3 bit 2 with internal pull-up; alternate function is external interrupt 0.
9 P3.3/INT1 bidirectional Port 3 bit 3 with internal pull-up; alternate function is external interrupt 1.
10 P3.4/T0 bidirectional Port 3 bit 4 with internal pull-up; alternate function is Timer 0 external input.
11 P3.5/T1 bidirectional Port 3 bit 5 with internal pull-up; alternate function is Timer 1 external input.
12 P3.6/WR bidirectional Port 3 bit 6 with internal pull-up; alternate function is external data memory write strobe.
13 P3.7/RD bidirectional Port 3 bit 7 with internal pull-up; alternate function is external data memory read strobe.
14 XTAL2 output Crystal oscillator output, the inversion of XTAL1.
15 XTAL1 input Crystal oscillator input; may be driven by an external clock.
16 VSS power_in Ground potential.
17 P4.0 bidirectional Port 4 bit 0, general purpose bit-addressable bi-directional I/O.
18 P2.0/A8 bidirectional Port 2 bit 0 with internal pull-up; also address bit A8 for external memory.
19 P2.1/A9 bidirectional Port 2 bit 1 with internal pull-up; also address bit A9 for external memory.
20 P2.2/A10 bidirectional Port 2 bit 2 with internal pull-up; also address bit A10 for external memory.
21 P2.3/A11 bidirectional Port 2 bit 3 with internal pull-up; also address bit A11 for external memory.
22 P2.4/A12 bidirectional Port 2 bit 4 with internal pull-up; also address bit A12 for external memory.
23 P2.5/A13 bidirectional Port 2 bit 5 with internal pull-up; also address bit A13 for external memory.
24 P2.6/A14 bidirectional Port 2 bit 6 with internal pull-up; also address bit A14 for external memory.
25 P2.7/A15 bidirectional Port 2 bit 7 with internal pull-up; also address bit A15 for external memory.
26 PSEN output Program store enable: strobes external ROM data onto the Port 0 bus during fetch and MOVC; no strobe during internal ROM access.
27 ALE output Address latch enable: separates the address from data on Port 0.
28 P4.1 bidirectional Port 4 bit 1, general purpose bit-addressable bi-directional I/O.
29 EA input External access enable: keep high to execute from internal ROM, low to force external ROM.
30 P0.7/AD7 bidirectional Port 0 bit 7, open-drain I/O (optional pull-up via P0UPR); multiplexed address/data bit 7.
31 P0.6/AD6 bidirectional Port 0 bit 6, open-drain I/O (optional pull-up via P0UPR); multiplexed address/data bit 6.
32 P0.5/AD5 bidirectional Port 0 bit 5, open-drain I/O (optional pull-up via P0UPR); multiplexed address/data bit 5.
33 P0.4/AD4 bidirectional Port 0 bit 4, open-drain I/O (optional pull-up via P0UPR); multiplexed address/data bit 4.
34 P0.3/AD3 bidirectional Port 0 bit 3, open-drain I/O (optional pull-up via P0UPR); multiplexed address/data bit 3.
35 P0.2/AD2 bidirectional Port 0 bit 2, open-drain I/O (optional pull-up via P0UPR); multiplexed address/data bit 2.
36 P0.1/AD1 bidirectional Port 0 bit 1, open-drain I/O (optional pull-up via P0UPR); multiplexed address/data bit 1.
37 P0.0/AD0 bidirectional Port 0 bit 0, open-drain I/O (optional pull-up via P0UPR); multiplexed address/data bit 0.
38 VDD power_in Power supply for operation, 2.4V to 5.5V.
39 P4.2/INT3 bidirectional Port 4 bit 2 general I/O or external interrupt 3 input.
40 P1.0/T2 bidirectional Port 1 bit 0 with internal pull-up; alternate function is Timer/Counter 2 external count input.
41 P1.1/T2EX bidirectional Port 1 bit 1 with internal pull-up; alternate function is Timer/Counter 2 reload/capture control.
42 P1.2 bidirectional Port 1 bit 2, bi-directional I/O with internal pull-up.
43 P1.3 bidirectional Port 1 bit 3, bi-directional I/O with internal pull-up.
44 P1.4 bidirectional Port 1 bit 4, bi-directional I/O with internal pull-up.

Key specifications

Parameter Value
Manufacturer Nuvoton Tech
Package TQFP-44(10x10)
Category Embedded Processors & Controllers
Pins 44

CAD (KiCad official)

  • Symbol: W78E054DFG
  • Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
  • 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: w78e054dfg-etched.step / w78e054dfg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); w78e054dfg.step / w78e054dfg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nuvoton Tech datasheet (89 pp, sha256 c3cab453b742088d, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF