component

W5200

Public Made by Adom

by adom

WIZNET Ethernet ICs, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsw5200factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

W5200

WIZNET · Ethernet ICs · QFN-48-EP(7x7)

W5200 from WIZNET, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XI input 25MHz crystal/oscillator input.
2 XO output 25MHz crystal output.
3 nFDXLED/M2 bidirectional Full Duplex/Collision LED output (low = full-duplex, high = half-duplex); also mode select bit M2, sampled only during reset (normal mode 111).
4 nSPDLED/M1 bidirectional Link speed LED output (low = 100Mbps, high = 10Mbps); also mode select bit M1, sampled only during reset (normal mode 111).
5 nLINKLED/M0 bidirectional Link LED output (low = link, high = no link, blink = TX/RX activity); also mode select bit M0, sampled only during reset (normal mode 111).
6 M3 input W5200 interface enable; this pin should be pulled up.
7 RSV passive Reserved pin; should be pulled down or tied to GND.
8 VCC1V8 power_in 1.8V power supply for the digital part.
9 GND power_in Digital ground.
10 GND power_in Digital ground.
11 VCC3V3A power_in 3.3V power supply for the analog part.
12 BIAS passive Bias resistor pin; connect a 28.7kΩ ±1% resistor to ground.
13 GNDA power_in Analog ground.
14 1V8O power_out 1.8V/200mA internal regulator output for core power (VCC1V8); needs a tantalum capacitor to GND and must not power other devices.
15 VCC3V3A power_in 3.3V power supply for the analog part.
16 XTALVDD passive Connect a 10.1uF capacitor to ground.
17 TXOP output Positive differential transmit output to the media.
18 TXON output Negative differential transmit output to the media.
19 GNDA power_in Analog ground.
20 RXIP input Positive differential receive input from the media.
21 RXIN input Negative differential receive input from the media.
22 GNDA power_in Analog ground.
23 VCC3V3A power_in 3.3V power supply for the analog part.
24 GNDA power_in Analog ground.
25 VCC1V8 power_in 1.8V power supply for the digital part.
26 GND power_in Digital ground.
27 VCC3V3 power_in 3.3V power supply for the digital part.
28 GND power_in Digital ground.
29 ANE input Auto negotiation enable (low = disable, high = enable).
30 DUP input Full duplex mode select (low = half duplex, high = full duplex), active only during reset.
31 SPD input Speed mode select (low = 10M, high = 100M), active only during reset; also listed among reserved pins.
32 RSV passive Reserved pin; should be pulled down or tied to GND.
33 RSV passive Reserved pin; should be pulled down or tied to GND.
34 RSV passive Reserved pin; should be pulled down or tied to GND.
35 RSV passive Reserved pin; should be pulled down or tied to GND.
36 RSV passive Reserved pin; should be pulled down or tied to GND.
37 RSV passive Reserved pin; should be pulled down or tied to GND.
38 RSV passive Reserved pin; should be pulled down or tied to GND.
39 RSV passive Reserved pin; should be pulled down or tied to GND.
40 nINT output Active-low interrupt output signalling that the W5200 needs MCU attention; cleared by writing IR or Sn_IR, all interrupts maskable.
41 nSCS input Active-low SPI slave select.
42 SCLK input SPI clock input.
43 MOSI input SPI master-out slave-in data input.
44 MISO output SPI master-in slave-out data output.
45 PWDN input Power down, active high (low = normal mode, high = power down).
46 nRST input Active-low reset; hold low at least 2us and wait at least 150ms after release for the PLL to stabilize.
47 VCC3V3 power_in 3.3V power supply for the digital part.
48 GND power_in Digital ground.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer WIZNET
Package QFN-48-EP(7x7)
Category Interface ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply voltage VDD 2.97 3.63 V Junction temperature is from -55°C to 125°C 77
High level input voltage VIH 2 5.5 V 77
Low level input voltage VIL -0.3 0.8 V 77
High level output voltage VOH 2.4 V IOH = 4 ~8 mA 77
Low level output voltage VOL 0.4 V IOL = 4 ~8mA 77
Input Current II 5 A VIN = VDD 77
DC Supply voltage (absolute maximum) VDD -0.5 3.63 V 77
DC input voltage (absolute maximum) VIN -0.5 5.5 V 5V tolerant 77
DC input current (absolute maximum) IIN 5 mA 77
Operating temperature TOP -40 85 C 77
Storage temperature TSTG -55 125 C 77
Reset Cycle Time TRC 2 us 78
nRST internal PLOCK TPL 150 ms 78
SCK Clock Frequency FSCK 80 MHz 79
SCK High Time TWH 6 ns 79
SCK Low Time TWL 6 ns 79
nSCS High Time TCS 5 ns 79
nSCS Hold Time TCSS 5 ns 79
Data In Setup Time TDS 3 ns 79
Data In Hold Time TDH 3 ns 79
Output Valid Time TOV 5 ns 79
Output Hold Time TOH 0 ns 79
nSCS High to Output Hi-Z TCHZ 5 ns 79
Power dissipation 100M Link 118 mA Vcc 3.3V, 25°C 77
Power dissipation 10M Link 98 mA Vcc 3.3V, 25°C 77
Power dissipation Loss Link 100 mA Vcc 3.3V, 25°C 77
Power dissipation 100M Transmitting 116 mA Vcc 3.3V, 25°C 77
Power dissipation 10M Transmitting 103 mA Vcc 3.3V, 25°C 77
Power dissipation Power Down mode 8 mA Vcc 3.3V, 25°C 77

CAD (KiCad official)

  • Symbol: W5200
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: w5200-etched.step / w5200-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); w5200.step / w5200.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WIZNET datasheet (84 pp, sha256 daaaefe42c213f34, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF