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W25Q80EWSNIG

Winbond Elec · NOR FLASH · SOIC-8

W25Q80EWSNIG from Winbond Elec, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 /CS input Chip Select Input; when high the device is deselected and DO/IO pins are high impedance, and /CS must track VCC at power-up.
2 DO (IO1) bidirectional Data Output (Data Input Output 1) used for standard and dual SPI instructions; it is high impedance when /CS is high.
3 /WP (IO2) bidirectional Write Protect Input (Data Input Output 2) that is active low and used as IO2 for Quad SPI; the /WP function is unavailable when QE=1.
4 GND power_in Ground reference for the device.
5 DI (IO0) bidirectional Data Input (Data Input Output 0) used for standard and dual SPI instructions, sampled on the rising edge of CLK.
6 CLK input Serial Clock Input that provides the timing for serial input and output operations.
7 /HOLD (IO3) bidirectional Hold Input (Data Input Output 3) that is active low and pauses device operation while /CS is low; used as IO3 for Quad SPI, and the /HOLD function is unavailable when QE=1.
8 VCC power_in Power Supply; the datasheet specifies a single 1.65V to 1.95V supply.

Key specifications

Parameter Value
Manufacturer Winbond Elec
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 1.65 1.95 V FR = 104MHz, fR = 50MHz 65
Ambient Temperature, Operating TA -40 85 °C Industrial 65
Supply Voltage VCC -0.6 2.5 V 65
Storage Temperature TSTG -65 150 °C 65
Electrostatic Discharge Voltage VESD -2000 2000 V Human Body Model 65
VCC (min) to /CS Low tVSL 10 µs 66
Time Delay Before Write Instruction tPUW 1 10 ms 66
Write Inhibit Threshold Voltage VWI 1 1.4 V 66
Input Capacitance CIN 6 pF VIN = 0V 67
Output Capacitance Cout 8 pF VOUT = 0V 67
Input Leakage ILI -2 2 µA 67
I/O Leakage ILO -2 2 µA 67
Standby Current ICC1 10 25 µA /CS = VCC, VIN = GND or VCC 67
Power-down Current ICC2 0.5 7.5 µA /CS = VCC, VIN = GND or VCC 67
Current Read Data / Dual /Quad 1MHz ICC3 1 3 mA C = 0.1 VCC / 0.9 VCC, DO = Open 67
Current Read Data / Dual /Quad 50MHz ICC3 4 6 mA C = 0.1 VCC / 0.9 VCC, DO = Open 67
Current Read Data / Dual Output / Quad Output Read 104MHz Icc3 6 8 mA C = 0.1 VCC / 0.9 VCC, DO = Open 67
Current Write Status Register Icc4 15 20 mA /CS = VCC 67
Current Page Program Icc5 15 20 mA /CS = VCC 67
Current Sector/Block Erase Icc6 15 20 mA /CS = VCC 67
Current Chip Erase Icc7 15 20 mA /CS = VCC 67
Input Low Voltage Vil -0.5 V 67
Output Low Voltage Vol 0.2 V Iol = 100 µA 67
Clock frequency for all instructions except Read Data (03h) FR 104 MHz 69
Clock frequency for Read Data instruction (03h) fR 50 MHz 69
Clock High, Low Time for all instructions except Read Data (03h) tCLH1, tCLL1 4 ns Clock high + clock low must be ≤ 1/fc 69
Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL 8 ns 69
/CS Active Setup Time relative to CLK tSLCH (tCSS) 5 ns 69
/CS Not Active Hold Time relative to CLK tCHSL 5 ns 69
Data In Setup Time tDVCH (tDSU) 2 ns 69
Data In Hold Time tCHDX (tDH) 5 ns 69
/CS Active Hold Time relative to CLK tCHSH 5 ns 69
/CS Not Active Setup Time relative to CLK tSHCH 5 ns 69
/CS Deselect Time (for Array Read - Array Read) tSHSL1 (tCSH) 10 ns 69
/CS Deselect Time (for Erase/Program - Read SR) / Volatile Status Register Write Time tSHSL2 (tCSH) 50 ns 69
Output Disable Time tSHQZ (tDIS) 7 ns 69
Clock Low to Output Valid tCLQV1 (tV1) 6 ns 69
Output Hold Time tCLQX (tHO) 0 ns 70
/HOLD Active Setup Time relative to CLK tHLCH 5 ns 70
/HOLD Active Hold Time relative to CLK tCHHH 5 ns 70
/HOLD Not Active Setup Time relative to CLK tHHCH 5 ns 70
/HOLD Not Active Hold Time relative to CLK tCHHL 5 ns 70
/HOLD to Output Low-Z tHHQX (tLZ) 7 ns 70
/HOLD to Output High-Z tHLQZ (tHZ) 12 ns 70
Write Protect Setup Time Before /CS Low tWHSL 20 ns Only applicable when SRP bit is set to 1 70
Write Protect Hold Time After /CS High tSHWL 100 ns Only applicable when SRP bit is set to 1 70
/CS High to Power-down Mode tDP 3 µs 70
/CS High to Standby Mode without ID Read tRES1 3 µs 70
/CS High to Standby Mode with ID Read tRES2 1.8 µs 70
/CS High to next Instruction after Suspend tSUS 20 µs 70
Write Status Register Time tW 1 15 ms 70
Byte Program Time (First Byte) tBP1 15 30 µs 70
Additional Byte Program Time (After First Byte) tBP2 2.5 5 µs 70
Page Program Time tPP 0.4 0.8 ms Maximum tPP specified with Page Program and 4KB Sector Erase (P/E) cycling condition 70
Sector Erase Time (4KB) tSE 45 400 ms 70
Block Erase Time (32KB) tBE1 150 800 ms 70
Block Erase Time (64KB) tBE2 180 1000 ms 70
Chip Erase Time tCE 3 10 s 70

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 9.1 8-Pin SOIC 208-mil (Package Code SS)............................................................................ 72 9.2 8-Pin SOIC 150-mil (Package Code SN)........................................ 4

CAD (KiCad official)

  • Symbol: W25Q80EWSNIG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: w25q80ewsnig-etched.step / w25q80ewsnig-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); w25q80ewsnig.step / w25q80ewsnig.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Winbond Elec datasheet (80 pp, sha256 4d31ad6252253663, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF